PDF M5M5Y5636TG-22 Data sheet ( Hoja de datos )

Número de pieza	M5M5Y5636TG-22
Descripción	18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Fabricantes	Mitsubishi
Logotipo
Hay una vista previa y un enlace de descarga de M5M5Y5636TG-22 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas
No Preview Available ! 2001.June Rev.0.0 Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. MITSUBISHI LSIs M5M5Y5636TG – 25,22,20 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM DESCRIPTION The M5M5Y5636TG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5Y5636TG operates on a single 1.8V power supply and are 1.8V CMOS compatible. FEATURES • Fully registered inputs and outputs for pipelined operation • Fast clock speed: 250, 225, and 200 MHz • Fast access time: 2.6, 2.8, 3.2 ns • Single 1.8V +150/-100mV power supply VDD • Separate VDDQ for 1.8V I/O • Individual byte write (BWa# - BWd#) controls may be tied LOW • Single Read/Write control pin (W#) • Echo Clock outputs track data output drivers • ZQ mode pin for user-selectable output drive strength • 2 User programmable chip enable inputs for easy depth expansion • Linear or Interleaved Burst Modes • JTAG boundary scan support APPLICATION High-end networking products that require high bandwidth, such as switches and routers. FUNCTION Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV), Byte Write Enables (BWa#, BWb#, BWc#, BWd#), Echo Clock outputs (CQ1, CQ1#, CQ2, CQ2#) and Read/Write (W#). Write operations are controlled by the eight Byte Write Enables (BWa# - BWd#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry. The Echo Clocks are delayed copies of the RAM clock, CLK. Echo Clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. The ZQ pin supplied with selectable impedance drivers, allows selection between nominal drive strength (ZQ LOW) for multi- drop bus application and low drive strength (ZQ floating or HIGH) point-to-point applications. The sense of two User-Programmable Chip Enable inputs (E2, E3), whether they function as active LOW or active HIGH inputs, is determined by the state of the programming inputs, EP2 and EP3. The Linear Burst order (LBO#) is DC operated pin. LBO# pin will allow the choice of either an interleaved burst, or a linear burst. All read, write and deselect cycles are initiated by the ADV Low input. Subsequent burst address can be internally generated as controlled by the ADV HIGH input. PACKAGE M5M5Y5636TG Bump 209(11X19) bump BGA Body Size 14mm X 22mm Bump Pitch 1mm PART NAME TABLE Part Name M5M5Y5636TG -25 M5M5Y5636TG -22 M5M5Y5636TG -20 Frequency 250MHz 225MHz 200MHz Access 2.6ns 2.8ns 3.2ns Cycle 4.0ns 4.4ns 5.0ns Active Current (max.) 400mA 380mA 360mA Standby Current (max.) 20mA 20mA 20mA 1 MITSUBISHI Advanced Information ELECTRIC M5M5Y5636TG REV.0.0 1 page MITSUBISHI LSIs M5M5Y5636TG – 25,22,20 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM Read Operation Pipelined Read Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3) are active, the write enable input signal (W#) is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. CLK E1# ADV W# BWx# ADD DQ CQ A Read A Deselect B Q(A) Read B CDE Q(B) Q(C) Read C Read D Read E 5 MITSUBISHI Advanced Information ELECTRIC M5M5Y5636TG REV.0.0 5 Page MITSUBISHI LSIs M5M5Y5636TG – 25,22,20 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM Pipelined Read Bank Switch with E1# Deselect CLK ADD A BCDE E1# E2# Bank1 E2 Bank2 DQ Bank1 CQ Bank1 CQ Bank1 + CQ Bank2 CQ Bank2 DQ Bank2 Q(A) Q(B) Q(C) Note10. E1# does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false. In some applications it may be appropriate to pause between banks; to deselect both SRAMs with E1# before resuming read operations. An E1# deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. Although the following drawing illustrates a E1# read pause upon switching from Bank 1 to Bank 2, a write to Bank 2 would have the same effect, causing the SRAM in Bank 2 to issue at least one clock before it is needed. Output Driver Impedance Control The ZQ pin of SRAMs supplied with selectable impedance drivers, allows selection between SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. 11 MITSUBISHI Advanced Information ELECTRIC M5M5Y5636TG REV.0.0 11 Page

Páginas	Total 27 Páginas
PDF Descargar	[ Datasheet M5M5Y5636TG-22.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
M5M5Y5636TG-20	18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM	Mitsubishi
M5M5Y5636TG-22	18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM	Mitsubishi
M5M5Y5636TG-25	18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM	Mitsubishi

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar