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M95256-VMW5T 데이터시트 PDF




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부품번호 M95256-VMW5T 기능
기능 256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
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M95256-VMW5T 데이터시트, 핀배열, 회로
M95256
M95128
256/128 Kbit Serial SPI Bus EEPROM
With High Speed Clock
PRELIMINARY DATA
s SPI Bus Compatible Serial Interface
s Supports Positive Clock SPI Modes
s 5 MHz Clock Rate (maximum)
s Single Supply Voltage:
– 4.5V to 5.5V for M95xxx
– 2.7V to 3.6V for M95xxx-V
– 2.5V to 5.5V for M95xxx-W
– 1.8V to 3.6V for M95xxx-R
s Status Register
s Hardware and Software Protection of the Status
Register
s BYTE and PAGE WRITE (up to 64 Bytes)
s Self-Timed Programming Cycle
s Resizeable Read-Only EEPROM Area
s Enhanced ESD Protection
s 100,000 Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
DESCRIPTION
These SPI-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 32K x 8 bits (M95256) and 16K x 8
bits (M95128), and operate down to 2.7 V (for the
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
VCC
14
1
TSSOP14 (DL)
169 mil width
8
1
SO8 (MW)
200 mil width
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
D
C
S
W
HOLD
M95xxx
VSS
Q
AI01789C
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/21




M95256-VMW5T pdf, 반도체, 판매, 대치품
M95256, M95128
Figure 4. Data and Clock Timing
CPOL CPHA
00
C
11
C
D or Q
MSB
LSB
AI01438
the memory device only allows the user to protect
a part of the memory, using the BPn bits of the
status register, in the Software Protected Mode
(SPM).
Hold (HOLD)
The HOLD pin is used to pause the serial
communications between the SPI memory and
controller, without losing bits that have already
been decoded in the serial sequence. For a hold
condition to occur, the memory device must
already have been selected (S = 0). The hold
condition starts when the HOLD pin is held low
while the clock pin (C) is also low (as shown in
Figure 5).
During the hold condition, the Q output pin is held
in its high impedance state, and the levels on the
input pins (D and C) are ignored by the memory
device.
It is possible to deselect the device when it is still
in the hold state, thereby resetting whatever
transfer had been in progress. The memory
remains in the hold state as long as the HOLD pin
is low. To restart communication with the device, it
is necessary both to remove the hold condition (by
taking HOLD high) and to select the memory (by
taking S low).
OPERATIONS
All instructions, addresses and data are shifted
serially in and out of the chip. The most significant
bit is presented first, with the data input (D)
sampled on the first rising edge of the clock (C)
after the chip select (S) goes low.
Every instruction starts with a single-byte code, as
summarized in Table 4. This code is entered via
the data input (D), and latched on the rising edge
of the clock input (C). To enter an instruction code,
the product must have been previously selected (S
held low). If an invalid instruction is sent (one not
contained in Table 4), the chip automatically
deselects itself.
Write Enable (WREN) and Write Disable (WRDI)
The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR
operation. The WREN instruction (write enable)
sets this latch, and the WRDI instruction (write
disable) resets it.
The latch becomes reset by any of the following
events:
– Power on
– WRDI instruction completion
– WRSR instruction completion
– WRITE instruction completion.
Table 3. Write Protection Control on the M95256 and M95128
W
SRWD
Bit
Mode
Status Register
Data Bytes
Protected Area
Unprotected Area
0 or 1 0 Software Writeable (if the WREN Software write protected Writeable (if the WREN
Protected instruction has set the
by the BPn of the status
instruction has set the
1 1 (SPM)
WEL bit)
register
WEL bit)
Hardware
Hardware write protected Writeable (if the WREN
0
1 Protected Hardware write protected by the BPn bits of the
instruction has set the
(HPM)
status register
WEL bit)
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M95256-VMW5T 전자부품, 판매, 대치품
Table 6. Write Protected Block Size
Status Register Bits
BP1
BP0
Protected Block
00
none
01
Upper quarter
10
Upper half
11
Whole memory
M95256, M95128
Array Addresses Protected
M95256
M95128
none
none
6000h - 7FFFh
3000h - 3FFFh
4000h - 7FFFh
2000h - 3FFFh
0000h - 7FFFh
0000h - 3FFFh
The size of the write-protection area applies
equally in SPM and HPM. The BP1 and BP0 bits
of the status register have the appropriate value
(see Table 6) written into them after the contents
of the protected area of the EEPROM have been
written.
The initial delivery state of the BP1 and BP0 bits is
00, indicating a write-protection size of 0.
Software Protected Mode (SPM)
The act of writing a non-zero value to the BP1 and
BP0 bits causes the Software Protected Mode
(SPM) to be started. All attempts to write a byte or
page in the protected area are ignored, even if the
Write Enable Latch is set. However, writing is still
allowed in the unprotected area of the memory
array and to the SRWD, BP1 and BP0 bits of the
status register, provided that the WEL bit is first
set.
Hardware Protected Mode (HPM)
The Hardware Protected Mode (HPM) offers a
higher level of protection, and can be selected by
setting the SRWD bit after pulling down the W pin
or by pulling down the W pin after setting the
SRWD bit. The SRWD is set by the WSR
instruction, provided that the WEL bit is first set.
The setting of the SRWD bit can be made
independently of, or at the same time as, writing a
new value to the BP1 and BP0 bits.
Once the device is in the Hardware Protected
Mode, the data bytes in the protected area of the
memory array, and the content of the status
register, are write-protected. The only way to re-
enable writing new values to the status register is
to pull the W pin high. This cause the device to
leave the Hardware Protected Mode, and to revert
to being in the Software Protected Mode. (The
value in the BP1 and BP0 bits will not have been
changed).
Further details of the operation of the Write Protect
pin (W) is given earlier, on page 3.
Typical Use of HPM and SPM
The W pin can be dynamically driven by an output
port of a microcontroller. It is also possible,
though, to connect it permanently to VSS (by a
solder connection, or through a pull-down
resistor). The manufacturer of such a printed
circuit board can take the memory device, still in its
initial delivery state, and can solder it directly on to
the board. After power on, the microcontroller can
be instructed to write the protected data into the
Figure 8. WRSR: Write Status Register Sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
INSTRUCTION
STATUS REG.
D 76543210
MSB
HIGH IMPEDANCE
Q
AI02282
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M95256-VMW5T

256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock

ST Microelectronics
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