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PDF PHN70308 Data sheet ( Hoja de datos )
| Número de pieza | PHN70308 | |
| Descripción | N-channel enhancement mode TrenchMOS transistor array | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
N-channel enhancement mode
TrenchMOS transistor array
Product specification
PHN70308
FEATURES
• 30 mΩ isolation transistor
• 80 mΩ spindle transistors
• TrenchMOS technology
• Logic level compatible
• Surface mount package
SYMBOL
isolation FET
S4
G4
D4
G7
S7
D1
G6
S6
D2
G5
S5
D3
G1
S1
G2
S2
G3
S3
QUICK REFERENCE DATA
VDS = 25 V
ID = 5 A
RDS(ON) ≤ 30 mΩ
(VGS = 10 V; isolation FET)
RDS(ON) ≤ 80 mΩ
(VGS = 10 V; spindle FETs)
GENERAL DESCRIPTION
This product is used to drive high performance, three phase brushless d.c. motors in computer disk drives.
The PHN70308 contains seven, n-channel enhancement mode trenchMOS transistors in a surface mounting plastic
package. Six of the transistors can be configured as a three phase bridge to drive the spindle of a disk drive motor.
The remaining transistor delivers power to the three phase bridge during normal operation. In the event of a power
failure occurring whilst the motor is still spinning, this transistor isolates the computer power supply from the back
emf generated by the motor.
The PHN70308 is supplied in the surface mounting SOT341-1 (SSOP28) package.
PINNING
SOT341-1 (SSOP28)
PIN
1,3
2
4
5,7
6
8
9,11
10
12
DESCRIPTION PIN
DESCRIPTION
drain 1
source 1
gate 1
drain 2
source 2
gate 2
drain 3
source 3
gate 3
16,17
18
20
21
23
24
26
27
13-15,19,22,25,28
source 4
gate 4
gate 5
source 5
gate 6
source 6
gate 7
source 7
drain 4
28
1
Top view
15
14
May 1999 1 Rev 1.000
1 page  
Philips Semiconductors
N-channel enhancement mode
TrenchMOS transistor array
Product specification
PHN70308
Drain current, ID (A)
1.0E-01
VDS = 5 V
1.0E-02
1.0E-03
minimum
1.0E-04
typical
1.0E-05
1.0E-06
0
0.5 1 1.5 2
Gate-source voltage, VGS (V)
2.5
Fig.5. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C
3
100 Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
10
tp = 10 us
100 us
1 ms
1
D.C.
10 ms
100 ms
0.1
0.1
1 10
Drain-Source Voltage, VDS (V)
100
Fig.6. Safe operating area (spindle FET) Tsp = 25˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
100 Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
10
D.C.
1
tp = 100 us
1 ms
10 ms
100 ms
0.1
0.1
1 10
Drain-Source Voltage, VDS (V)
100
Fig.7. Safe operating area (isolation FET) Tsp = 25˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Transient thermal impedance, Zth j-a (K/W)
100
D = 0.5
0.2
10
0.1
0.05
1 0.02
0.1 single pulse
P
D
D = tp/T
tp
0.01
1E-06
1E-05
1E-04
1E-03
1E-02
Pulse width, tp (s)
T
1E-01 1E+00 1E+01
Fig.8. Transient thermal impedance (spindle FET).
Zth j-sp = f(t); parameter D = tp/T
Transient thermal impedance, Zth j-a (K/W)
100
D = 0.5
10
0.2
0.1
1 0.05
0.02
single pulse
0.1
P
D
D = tp/T
tp
0.01
1E-06
1E-05
1E-04
1E-03 1E-02
Pulse width, tp (s)
T
1E-01 1E+00 1E+01
Fig.9. Transient thermal impedance (isolation FET).
Zth j-sp = f(t); parameter D = tp/T
Drain Current, ID (A)
8
VGS = 10 V
7
6
4.5 V
Tj = 25 C
5
3.6 V
4
3.4 V
3
3.2 V
2
3V
1 2.8 V
2.6 V
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Fig.10. Typical output characteristics (spindle FET)
Tj = 25 ˚C; ID = f(VDS); parameter VGS
May 1999 5 Rev 1.000
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PHN70308.PDF ] | |
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