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PDF PHT6NQ10T Data sheet ( Hoja de datos )

Número de pieza PHT6NQ10T
Descripción N-channel TrenchMOS transistor
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
N-channel TrenchMOStransistor
Product specification
PHT6NQ10T
FEATURES
’Trench’ technology
• Low on-state resistance
• Fast switching
• Low thermal resistance
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 100 V
ID = 6.5 A
RDS(ON) 90 m
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect transistor in a plastic
envelope
using
trench
technology.
Applications:-
• Motor and relay drivers
• d.c. to d.c. converters
The PHT6NQ10T is supplied in the
SOT223 surface mounting
package.
PINNING
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
SOT223
4
123
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 k
Continuous drain current (dc) Tsp = 25 ˚C
Tamb = 25 ˚C
Continuous drain current (dc) Tsp = 100 ˚C
Tamb = 100 ˚C
Pulsed drain current
Total power dissipation
Operating junction and
Tsp = 25 ˚C
Tamb = 25 ˚C
storage temperature
MIN.
-
-
-
-
-
-
-
-
-
-
- 65
MAX.
100
100
± 20
6.5
3
4.1
1.9
26
8.3
1.8
150
UNIT
V
V
V
A
A
A
A
A
W
W
˚C
THERMAL RESISTANCES
SYMBOL
Rth j-sp
Rth j-amb
PARAMETER
Thermal resistance junction to
solder point
Thermal resistance junction to
ambient
CONDITIONS
surface mounted, FR4
board
surface mounted, FR4
board
TYP.
12
70
MAX.
15
-
UNIT
K/W
K/W
August 1999
1
Rev 1.000

1 page




PHT6NQ10T pdf
Philips Semiconductors
N-channel TrenchMOStransistor
Product specification
PHT6NQ10T
Gate-source voltage, VGS (V)
15
14 ID = 6A
13
12
Tj = 25 C
11
10 VDD = 20 V
9
8
7
6
5
4
3
2
1
0
VDD = 80 V
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Source-Drain Diode Current, IF (A)
6
VGS = 0 V
5
4
150 C
3
Tj = 25 C
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
5
Rev 1.000

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