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Número de pieza | PHW50NQ15T | |
Descripción | N-channel TrenchMOS transistor | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PHW50NQ15T (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
No Preview Available ! Philips Semiconductors
N-channel TrenchMOS™ transistor
Product specification
PHW50NQ15T
FEATURES
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 150 V
ID = 50 A
RDS(ON) ≤ 35 mΩ
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope using ’trench’
technology.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PHW50NQ15T is supplied in
the SOT429 (TO247) conventional
leaded package.
PINNING
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
SOT429 (TO247)
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
150
150
± 20
50
36
200
250
175
UNIT
V
V
V
A
A
A
W
˚C
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 47 A;
energy
tp = 100 µs; Tj prior to avalanche = 25˚C;
VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer
to fig;15
IAS Non-repetitive avalanche
current
MIN.
-
MAX.
460
UNIT
mJ
- 50 A
August 1999
1
Rev 1.000
1 page Philips Semiconductors
N-channel TrenchMOS™ transistor
Product specification
PHW50NQ15T
Gate-source voltage, VGS (V)
15
14 ID = 50A
13
12
Tj = 25 C
11
10
9
8
7
6
5
4
3
2
1
0
VDD = 30 V
VDD = 120 V
0 10 20 30 40 50 60 70 80 90
Gate charge, QG (nC)
100
Fig.13. Typical turn-on gate-charge characteristics
VGS = f(QG)
Source-Drain Diode Current, IF (A)
50
VGS = 0 V
45
40
35
175 C
30
Tj = 25 C
25
20
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
Source-Drain Voltage, VSDS (V)
1.2
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Maximum Avalanche Current, IAS (A)
100
25 C
10
Tj prior to avalanche = 150 C
1
0.001
0.01 0.1
1
Avalanche time, tAV (ms)
10
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
August 1999
5
Rev 1.000
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet PHW50NQ15T.PDF ] |
Número de pieza | Descripción | Fabricantes |
PHW50NQ15T | N-channel TrenchMOS transistor | NXP Semiconductors |
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