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Número de pieza | PHW7N60 | |
Descripción | PowerMOS transistor | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PHW7N60 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
No Preview Available ! Philips Semiconductors
PowerMOS transistor
Product specification
PHW7N60
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope featuring high
avalanche energy capability, stable
off-state characteristics, fast
switching and high thermal cycling
performance with low thermal
resistance. Intended for use in
Switched Mode Power Supplies
(SMPS), motor control circuits and
general purpose switching
applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
600
7
147
1.2
UNIT
V
A
W
Ω
PINNING - SOT429 (TO247)
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
PIN CONFIGURATION
1 23
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
ID Continuous drain current
IDM
PD
∆PD/∆Tmb
VGS
EAS
IAS
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Single pulse avalanche
energy
Peak avalanche current
Tj, Tstg
Operating junction and
storage temperature range
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
Tmb > 25 ˚C
VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
7
4.5
28
147
1.176
± 30
570
7
150
UNIT
A
A
A
W
W/K
V
mJ
A
˚C
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MIN. TYP. MAX. UNIT
- - 0.85 K/W
- 45 - K/W
June 1997
1
Rev 1.000
1 page Philips Semiconductors
PowerMOS transistor
Product specification
PHW7N60
15 VGS, Gate-Source voltage (Volts)
ID = 6.2 A
Tj = 25 C
240 V
120 V
10
PHP6N60
VDD = 360 V
5
0
0 50 100 150
Qg, Gate charge (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
1000 Switching times (ns)
VDD = 300 V
VGS = 10 V
RD = 47 Ohms
ID = 6.2 A
Tj = 25 C
td(off)
100
tf
tr
PHP6N60
td(on)
10
0 10 20 30 40 50
RG, Gate resistance (Ohms)
Fig.14. Typical switching times.
td(on), tr, td(off), tf = f(RG)
60
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100
-50 0 50 100
Tj, Junction temperature (C)
150
Fig.15. Normalised drain-source breakdown voltage.
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
20 IF, Source-Drain diode current (Amps)
VGS = 0 V
15
PHP6N60
10
150 C
Tj = 25 C
5
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VSDS, Source-Drain voltage (Volts)
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
EAS, Normalised unclamped inductive energy (%)
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140
Starting Tj ( C)
Fig.17. Normalised unclamped inductive energy.
EAS% = f(Tj)
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.18. Unclamped inductive test circuit.
EAS = 0.5 ⋅ LID2 ⋅ V(BR)DSS/(V(BR)DSS − VDD)
June 1997
5
Rev 1.000
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet PHW7N60.PDF ] |
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