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Número de pieza PHW8N50E
Descripción PowerMOS transistors Avalanche energy rated
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
Product specification
PHP8N50E, PHB8N50E, PHW8N50E
FEATURES
• Repetitive Avalanche Rated
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 500 V
ID = 8.5 A
RDS(ON) 0.85
GENERAL DESCRIPTION
N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies,
T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching
applications.
The PHP8N50E is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHW8N50E is supplied in the SOT429 (TO247) conventional leaded package.
The PHB8N50E is supplied in the SOT404 surface mounting package.
PINNING
SOT78 (TO220AB) SOT404
SOT429 (TO247)
PIN DESCRIPTION
1 gate
tab
tab
2 drain1
3 source
tab drain
1 23
2
13
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total dissipation
Operating junction and
storage temperature range
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 k
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
500
500
± 30
8.5
5.4
34
147
150
UNIT
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin 2 of the SOT404 package.
December 1998
1
Rev 1.300

1 page




PHW8N50E pdf
Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
Product specification
PHP8N50E, PHB8N50E, PHW8N50E
25 ID, Drain current (Amps)
VDS > ID x RDS(on)max
20
PHP8N50
15
10
5
Tj = 150 C
Tj = 25 C
0
02468
VGS, Gate-Source voltage (Volts)
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
10
gfs, Transconductance (S)
10
VDS > ID x RDS(on)max
Tj = 25 C
8
6
PHP8N50
150 C
4
2
0
0 5 10 15 20
ID, Drain current (A)
Fig.8. Typical transconductance.
gfs = f(ID); parameter Tj
25
a
2
Normalised RDS(ON) = f(Tj)
1
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 4.25 A; VGS = 10 V
VGS(TO) / V
4
3
2
max.
typ.
min.
1
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
1E-01 ID / A
SUB-THRESHOLD CONDUCTION
1E-02
1E-03
2 % typ 98 %
1E-04
1E-05
1E-06
01234
VGS / V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
10000 Junction capacitances (pF)
PHP8N50
1000
Ciss
100 Coss
Crss
10
1 10 100
VDS, Drain-Source voltage (Volts)
1000
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
December 1998
5
Rev 1.300

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