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부품번호 | PHW8ND50E 기능 |
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기능 | PowerMOS transistors FREDFET/ Avalanche energy rated | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
Philips Semiconductors
Product specification
PowerMOS transistors
PHP8ND50E, PHB8ND50E, PHW8ND50E
FREDFET, Avalanche energy rated
FEATURES
• Repetitive Avalanche Rated
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
• Fast reverse recovery diode
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 500 V
ID = 8.5 A
RDS(ON) ≤ 0.85 Ω
trr = 180 ns
GENERAL DESCRIPTION
N-channel, enhancement mode field-effect power transistor, incorporating a Fast Recovery Epitaxial Diode (FRED).
This gives improved switching performance in half bridge and full bridge converters making this device particularly
suitable for inverters, lighting ballasts and motor control circuits.
The PHP8ND50E is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHW8ND50E is supplied in the SOT429 (TO247) conventional leaded package.
The PHB8ND50E is supplied in the SOT404 surface mounting package.
PINNING
SOT78 (TO220AB) SOT404
SOT429 (TO247)
PIN DESCRIPTION
1 gate
tab
tab
2 drain1
3 source
tab drain
1 23
2
13
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total dissipation
Operating junction and
storage temperature range
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 kΩ
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
500
500
± 30
8.5
5.4
34
147
150
UNIT
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin 2 of the SOT404 package.
August 1998
1
Rev 1.100
Philips Semiconductors
PowerMOS transistors
FREDFET, Avalanche energy rated
Product specification
PHP8ND50E, PHB8ND50E, PHW8ND50E
120 PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
ID%
120
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
ID / A
100
10
RDS(ON) = VDS/ID
1 DC
BUK457-500B
tp = 10 us
100 us
1 ms
10 ms
100 ms
0.1
1
10 100 1000
VDS / V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
1 Zth j-mb, Transient thermal impedance (K/W) PHP6N60
D = 0.5
0.2
0.1 0.1
0.05
0.02
0.01
single pulse
PD tp
D
=
tp
T
0.0011us
10us 100us 1ms
Tt
10ms 100ms
tp, pulse width (s)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
1s
30 ID, Drain current (Amps)
Tj = 25 C
25
20
15
10
5
PHP8N50
10 V
7V
6.5 V
6V
5.5 V
5V
VGS = 4.5 V
0
0 5 10 15 20 25
VDS, Drain-Source voltage (Volts)
Fig.5. Typical output characteristics.
ID = f(VDS); parameter VGS
30
2 RDS(on), Drain-Source on resistance (Ohms) PHP8N50
4.5 V
5 V 5.5 V VGS = 6 V Tj = 25 C
1.5
6.5 V
7V
1 10 V
0.5
0
0 5 10 15 20
ID, Drain current (Amps)
Fig.6. Typical on-state resistance.
RDS(ON) = f(ID); parameter VGS
25
August 1998
4
Rev 1.100
4페이지 Philips Semiconductors
PowerMOS transistors
FREDFET, Avalanche energy rated
Product specification
PHP8ND50E, PHB8ND50E, PHW8ND50E
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
10,3
max
3,7
2,8
1,3
4,5
max
5,9
min
15,8
max
3,0 max
not tinned
1,3
max 1 2 3
(2x)
3,0
13,5
min
0,9 max (3x)
2,54 2,54
0,6
2,4
Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
August 1998
7
Rev 1.100
7페이지 | |||
구 성 | 총 10 페이지수 | ||
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PHW8ND50E | PowerMOS transistors FREDFET/ Avalanche energy rated | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |