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What is PHX3055L?

This electronic component, produced by the manufacturer "NXP Semiconductors", performs the same function as "PowerMOS transistor Logic level FET".


PHX3055L Datasheet PDF - NXP Semiconductors

Part Number PHX3055L
Description PowerMOS transistor Logic level FET
Manufacturers NXP Semiconductors 
Logo NXP Semiconductors Logo 


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Philips Semiconductors
PowerMOS transistor
Logic level FET
Preliminary specification
PHX3055L
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic full-pack envelope. The
device features high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general purpose switching
applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
60
9.4
28
0.18
UNIT
V
A
W
PINNING - SOT186A
PIN DESCRIPTION
1 gate
2 drain
3 source
case isolated
PIN CONFIGURATION
case
12 3
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
ID Continuous drain current
IDM
PD
PD/Ths
VGS
VGSM
EAS
IAS
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Non-repetitive gate source
voltage
Single pulse avalanche
energy
Peak avalanche current
Tj, Tstg
Operating junction and
storage temperature range
Ths = 25 ˚C; VGS = 10 V
Ths = 100 ˚C; VGS = 10 V
Ths = 25 ˚C
Ths = 25 ˚C
Ths > 25 ˚C
tp50µs
VDD 50 V; starting Tj = 25˚C; RGS = 50 ;
VGS = 10 V
VDD 50 V; starting Tj = 25˚C; RGS = 50 ;
VGS = 10 V
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
9.4
5.9
26
28
0.22
± 15
± 20
25
6
150
UNIT
A
A
A
W
W/K
V
V
mJ
A
˚C
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
Visol R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal
three terminals to external
waveform;
heatsink
R.H. 65% ; clean and dustfree
Cisol Capacitance from T2 to external f = 1 MHz
heatsink
MIN. TYP. MAX. UNIT
- 2500 V
- 10 - pF
October 1997
1
Rev 1.000

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PHX3055L equivalent
Philips Semiconductors
PowerMOS transistor
Logic level FET
Preliminary specification
PHX3055L
VGS, Gate-Source voltage (Volts)
15
ID = 10 A
Tj = 25 C
VDS = 30 V
10
PHP3055E
48 V
5
0
0 5 10 15
Qg, Gate charge (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Switching times (ns)
1000
VDD = 30 V
VGS = 10 V
RD = 2.7 Ohms
ID = 10 A
100 Tj = 25 C
tr
td(off)
tf
10
td(on)
PHP3055E
1
0 20 40 60 80
RG, Gate resistance (Ohms)
Fig.14. Typical switching times.
td(on), tr, td(off), tf = f(RG)
100
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100
-50 0 50 100
Tj, Junction temperature (C)
150
Fig.15. Normalised drain-source breakdown voltage.
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
IF, Source-drain diode current (Amps)
20
VGS = 0 V
PHP3055E
15
Tj = 175 C
Tj = 25 C
10
5
0
0 0.5 1
VSDS, Source-drain voltage (Volts)
1.5
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
EAS, Normalised unclamped inductive energy (%)
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140
Starting Tj ( C)
Fig.17. Normalised unclamped inductive energy.
EAS% = f(Tj)
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.18. Unclamped inductive test circuit.
EAS = 0.5 LID2 V(BR)DSS/(V(BR)DSS VDD)
October 1997
5
Rev 1.000


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Part Details

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