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PDF PHX4N50E Data sheet ( Hoja de datos )

Número de pieza PHX4N50E
Descripción PowerMOS transistor Isolated version of PHP4N50E
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
PowerMOS transistor
Isolated version of PHP4N50E
Objective specification
PHX4N50E
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a full
pack, plastic envelope featuring high
avalanche energy capability, stable
blocking voltage, fast switching and
high thermal cycling performance
with low thermal resistance. Intended
for use in Switched Mode Power
Supplies (SMPS), motor control
circuits and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
500
2.9
30
1.5
UNIT
V
A
W
PINNING - SOT186A
PIN DESCRIPTION
1 gate
2 drain
3 source
case isolated
PIN CONFIGURATION
case
12 3
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
IDM
IDR
IDRM
Ptot
Tstg
Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
RGS = 20 k
Ths = 25 ˚C
Ths = 100 ˚C
Ths = 25 ˚C
Ths = 25 ˚C
Ths = 25 ˚C
Ths = 25 ˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
WDSR1
Drain-source repetitive
unclamped inductive turn-off
energy
CONDITIONS
ID = 5.3 A; VDD 50 V; VGS = 10 V;
RGS = 50
Tj = 25˚C prior to surge
Tj = 100˚C prior to surge
ID = 5.3 A; VDD 50 V; VGS = 10 V;
RGS = 50 ; Tj 150 ˚C
MIN.
-
-
-
-
-
-
-
-
-
-55
-
MIN.
-
-
-
MAX.
500
500
30
2.9
1.8
11.6
2.9
11.6
30
150
150
MAX.
280
44
7.4
UNIT
V
V
V
A
A
A
A
A
W
˚C
˚C
UNIT
mJ
mJ
mJ
Pulse width and frequency limited by Tj(max)
November 1996
1
Rev 1.000

1 page




PHX4N50E pdf
Philips Semiconductors
PowerMOS transistor
Objective specification
PHX4N50E
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
© Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
November 1996
5
Rev 1.000

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