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PHX8N50E 데이터시트 PDF




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부품번호 PHX8N50E 기능
기능 PowerMOS transistors Avalanche energy rated
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PHX8N50E 데이터시트, 핀배열, 회로
Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
Product specification
PHX8N50E
FEATURES
• Repetitive Avalanche Rated
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Isolated package
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 500 V
ID = 4.2 A
RDS(ON) 0.85
GENERAL DESCRIPTION
N-channel, enhancement mode
field-effect power transistor,
intended for use in off-line switched
mode power supplies, T.V. and
computer monitor power supplies,
d.c. to d.c. converters, motor control
circuits and general purpose
switching applications.
The PHX8N50E is supplied in the
SOT186A full pack, isolated
package.
PINNING
PIN DESCRIPTION
1 gate
2 drain
3 source
case isolated
SOT186A
case
12 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total dissipation
Operating junction and
storage temperature range
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 k
Ths = 25 ˚C; VGS = 10 V
Ths = 100 ˚C; VGS = 10 V
Ths = 25 ˚C
Ths = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
500
500
± 30
4.2
2.7
34
37
150
UNIT
V
V
V
A
A
A
W
˚C
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
EAS
EAR
IAS, IAR
Non-repetitive avalanche
energy
Unclamped inductive load, IAS = 7.4 A;
tp = 0.22 ms; Tj prior to avalanche = 25˚C;
VDD 50 V; RGS = 50 ; VGS = 10 V; refer
to fig:17
Repetitive avalanche energy1 IAR = 8.5 A; tp = 2.5 µs; Tj prior to
avalanche = 25˚C; RGS = 50 ; VGS = 10 V;
refer to fig:18
Repetitive and non-repetitive
avalanche current
MIN.
-
-
-
MAX.
531
13
8.5
UNIT
mJ
mJ
A
1 pulse width and repetition rate limited by Tj max.
December 1998
1
Rev 1.300




PHX8N50E pdf, 반도체, 판매, 대치품
Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
120 PD%
110
Normalised Power Derating
with heatsink compound
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Ths / C
Fig.1. Normalised power dissipation.
PD% = 100PD/PD 25 ˚C = f(Ths)
ID%
120
110
Normalised Current Derating
with heatsink compound
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Ths / C
Fig.2. Normalised continuous drain current.
ID% = 100ID/ID 25 ˚C = f(Ths); conditions: VGS 10 V
100 ID, Drain current (Amps)
10 RDS(ON) = VDS/ID
1
DC
0.1
PHX5N50
tp = 10 us
100 us
1 ms
10 ms
100 ms
0.01
1
10 100 1000
VDS, Drain-source voltage (Volts)
10000
Fig.3. Safe operating area. Ths = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Product specification
PHX8N50E
10 Zth j-hs, Transient thermal impedance (K/W) PHX4N60
D = 0.5
1 0.2
0.1
0.05
0.1 0.02
0.01
PD tp
D
=
tp
T
single pulse
Tt
0.0011us
10us 100us 1ms
10ms 100ms
tp, pulse width (s)
Fig.4. Transient thermal impedance.
Zth j-hs = f(t); parameter D = tp/T
1s
30 ID, Drain current (Amps)
Tj = 25 C
25
20
15
10
5
PHP8N50
10 V
7V
6.5 V
6V
5.5 V
5V
VGS = 4.5 V
0
0 5 10 15 20 25
VDS, Drain-Source voltage (Volts)
Fig.5. Typical output characteristics.
ID = f(VDS); parameter VGS
30
2 RDS(on), Drain-Source on resistance (Ohms) PHP8N50
4.5 V
5 V 5.5 V VGS = 6 V Tj = 25 C
1.5
6.5 V
7V
1 10 V
0.5
0
0 5 10 15 20
ID, Drain current (Amps)
Fig.6. Typical on-state resistance.
RDS(ON) = f(ID); parameter VGS
25
December 1998
4
Rev 1.300

4페이지










PHX8N50E 전자부품, 판매, 대치품
Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Recesses (2x)
2.5
0.8 max. depth
10.3
max
3.2
3.0
3 max.
not tinned
13.5
min.
0.4 M
12 3
5.08
4.6
max
2.9 max
2.8
15.8 19
max. max.
seating
plane
6.4
15.8
max
3
2.5
0.6
2.54 0.5
2.5
Product specification
PHX8N50E
1.0 (2x)
0.9
0.7
1.3
Fig.19. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
December 1998
7
Rev 1.300

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부품번호상세설명 및 기능제조사
PHX8N50E

PowerMOS transistors Avalanche energy rated

NXP Semiconductors
NXP Semiconductors

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