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기능 N-CHANNEL ENHANCEMENT-MODE TMOS MOSFET
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MGSF1N02LT1 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MGSF1N02LT1/D
Low rDS(on) Small-Signal MOSFETs
TMOS Single N-Channel
Field Effect Transistors
Part of the GreenLinePortfolio of devices with energy–
conserving traits.
These miniature surface mount MOSFETs utilize Motorola’s
High Cell Density, HDTMOS process. Low rDS(on) assures
minimal power loss and conserves energy, making this device
ideal for use in space sensitive power management circuitry.
Typical applications are dc–dc converters and power manage-
ment in portable and battery–powered products such as
computers, printers, PCMCIA cards, cellular and cordless
telephones.
Low rDS(on) Provides Higher Efficiency and Extends Battery
Life
Miniature SOT–23 Surface Mount Package Saves Board
Space
1
GATE
3 DRAIN
2 SOURCE
MGSF1N02LT1
Motorola Preferred Device
N–CHANNEL
ENHANCEMENT–MODE
TMOS MOSFET
3
1
2
CASE 318–08, Style 21
SOT–23 (TO–236AB)
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C
Drain Current — Pulsed Drain Current (tp 10 µs)
Total Power Dissipation @ TA = 25°C
Operating and Storage Temperature Range
Thermal Resistance — Junction–to–Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MGSF1N02LT1
78mm embossed tape
3000
MGSF1N02LT3
138mm embossed tape
10,000
GreenLine is a trademark of Motorola, Inc.
HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
©MMotootorroollaa, SInmc. 1a9ll96Signal Transistors, FETs and Diodes Device Data
Symbol
VDSS
VGS
ID
IDM
PD
TJ, Tstg
RθJA
TL
Value
20
± 20
750
2000
225
– 55 to 150
625
260
Unit
Vdc
Vdc
mA
mW
°C
°C/W
°C
1




MGSF1N02LT1 pdf, 반도체, 판매, 대치품
MGSF1N02LT1
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.035
0.9
0.079
2.0
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
drain pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by TJ(max), the maximum rated junction temperature of the
die, RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA. Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD =
150°C – 25°C
556°C/W
= 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
4 Motorola Small–Signal Transistors, FETs and Diodes Device Data

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