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MH16D72AKLB-75 데이터시트 PDF




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부품번호 MH16D72AKLB-75 기능
기능 1 /207.959 /552-BIT (16 /777 /216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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MH16D72AKLB-75 데이터시트, 핀배열, 회로
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH16D72AKLB is 16777216 - word x 72-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 9 industry standard 16M x 8 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
93pin 1pin
FEATURES
Type name
Max.
Frequency
MH16D72AKLB-75
MH16D72AKLB-10
133MHz
100MHz
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
- Utilizes industry standard 16M X 8 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CK0 and /CK0)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-9
- SSTL_2 Interf ace
- Module 1bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
APPLICATION
Main memoryunit for PC, PCserver
144pin 52pin
145pin 53pin
184pin 92pin
MIT-DS-0397-1.1
MITSUBISHI ELECTRIC
24.Nov.2000
1




MH16D72AKLB-75 pdf, 반도체, 판매, 대치품
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN FUNCTION
SYMBOL
TYPE
CK0,/CK0
Input
CKE0
Input
DESCRIPTION
Clock: CK0 and /CK0 are dif f erential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK0 and negativ e
edge of /CK0. Output (read) data is ref erenced to the crossings of CK0 and
/CK0 (both directions of c rossing).
Clock Enable: CKE0 controls SDRAM internal clock. When CKE0 is low, the
internal clock f or the f ollowing cy c le is ceased. CKE0 is also used to select
auto / self ref resh. After self ref resh mode is started, CKE0 becomes
asy nchronous input. Self ref resh is maintained as long as CKE0 is low.
/S0
/RAS, /CAS, /WE
A0-11
Input
Input
Input
Phy s ical Bank Select: When /S0 is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specif y the Row / Column Address in conjunction with BA0,1. The Row
Address is specif ied by A0-11. The Column Address is specif ied by A0-9.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is perf ormed. When A10 is high at a precharge
command, all banks are precharged.
BA0,1
DQ 0-64
CB 0-7
DQS0-8
DM0-8
Input
Bank Address: BA0,1 specifies one of four banks in SDRAM to which a command is applied. BA0,1
must be set with ACT, PRE, READ, WRITE commands.
Input / Output Data Input/Output: Data bus
Input / Output Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data.
Input
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write
latency of one clock once the write command is registered into the SDRAM.
Vdd, Vss
Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Vddspd
Vref
RESET
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
Power Supply Power Supply for SPD
Input
SSTL_2 reference voltage.
Input
This signal is asy nchronous and is driv en low to the register in order to
guarantee the register outputs are low.
SDA
SCL
SA0-2
VDDID
Input / Output This bidirectional pin is used to transf er data into or out of the SPD EEPROM.
A resistor must be connected f rom the SDA bus line to VDD to act as a pullup.
Input
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor
may be connected f rom the SCL bus time to VDD to act as a pullup.
These signals are tied at the system planar to either VSS or VDD to conf igure
the serial SPD EEPROM address range.
VDD identif ication f lag
MIT-DS-0397-1.1
MITSUBISHI ELECTRIC
24.Nov.2000
4

4페이지










MH16D72AKLB-75 전자부품, 판매, 대치품
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
Current State /S /RAS /CAS /WE
Address
IDLE
H X X XX
L H H HX
L H H L BA
L H L X BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
ROW ACTIVE H X X X X
L H H HX
L H H L BA
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op-Code,
Mode-Add
READ
H X X XX
(Auto-
L H H HX
Precharge L H H L BA
Di sa b l e d )
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
L L L L Mode-Add
Command
Action
DESEL NOP
NOP
NOP
TERM
ILLEGAL
READ / WRITE ILLEGAL
ACT
Bank Active, Latch RA
PRE / PREA NOP
REFA
Auto-Refresh
MRS
Mode Register Set
Notes
2
2
4
5
5
DESEL NOP
NOP
NOP
TERM
NOP
Begin Read, Latch CA,
READ / READA
Determine Auto-Precharge
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
ACT
Bank Active / ILLEGAL
PRE / PREA Precharge / Precharge All
REFA
ILLEGAL
MRS
ILLEGAL
2
DESEL NOP (Continue Burst to END)
NOP
NOP (Continue Burst to END)
TERM
Terminate Burst
Terminate Burst, Latch CA,
READ / READA Begin New Read, Determine
Auto-Precharge
WRIT E
WRITEA
ILLEGAL
3
ACT
Bank Active / ILLEGAL
2
PRE / PREA Terminate Burst, Precharge
REFA
ILLEGAL
MRS
ILLEGAL
MIT-DS-0397-1.1
MITSUBISHI ELECTRIC
24.Nov.2000
7

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MH16D72AKLB-75

1 /207.959 /552-BIT (16 /777 /216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Mitsubishi
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