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MH16S64AMA-8 데이터시트 PDF




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부품번호 MH16S64AMA-8 기능
기능 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
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MH16S64AMA-8 데이터시트, 핀배열, 회로
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64AMA is 16777216 - word by 64-bit
Synchronous DRAM module. This consists of sixteen
industry standard 16Mx4 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
-8 125MHz
CLK Access Time
(Component SDRAM)
6ns(CL=3)
-10 100MHz
8ns(CL=3)
85pin 1pin
94pin
95pin
10pin
11pin
-12 83MHz
8ns(CL=3)
Utilizes industry standard 16M x 4 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 125MHz/100MHz/83MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
124pin 40pin
125pin 41pin
168pin 84pin
APPLICATION
main memory or graphic memory in computer systems
MIT-DS-0127-0.0
MITSUBISHI
ELECTRIC
( 1 / 52 )
4. Mar.1997




MH16S64AMA-8 pdf, 반도체, 판매, 대치품
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
0 Defines # bytes written into serial memory at module mfgr
128
1 Total # bytes of SPD memory device
256 Bytes
2 Fundamental memory type
SDRAM
3 # Row Addresses on this assembly
A0-A11
4 # Column Addresses on this assembly
A0-A9
5 # Module Banks on this assembly
1BANK
6 Data Width of this assembly...
x64
7 ... Data Width continuation
0
8 Voltage interface standard of this assembly
LVTTL
9 SDRAM Cycletime at Max. Supported CAS Latency (CL). -8
8ns
Cycle time for CL=3
-10 10ns
-12 12ns
10
SDRAM Access from Clock
-8 6ns
tAC for CL=3
-10 8ns
-12 8ns
11 DIMM Configuration type (Non-parity,Parity,ECC)
Non-PARITY
12 Refresh Rate/Type
self refresh(15.625uS)
13 SDRAM width,Primary DRAM
x4
14 Error Checking SDRAM data width
N/A
15 Minimum Clock Delay,Back to Back Random Column Addresses
1
16 Burst Lengths Supported
1/2/4/8
17 # Banks on Each SDRAM device
4bank
18 CAS# Latency
CL=2/3
19 CS# Latency
0
20 Write Latency
0
21 SDRAM Module Attributes
non-buffered,non-registered
22 SDRAM Device Attributes:General
Precharge All,Auto precharge
23
SDRAM Cycle time(2nd highest CAS latency)
-8
13ns
Cycle time for CL=2
-10 14ns
-12 15ns
24 SDRAM Access form Clock(2nd highest CAS latency) -8
7ns
tAC for CL=2
-10 8ns
-12 9ns
25
SDRAM Cycle time(3rd highest CAS latency)
-8
N/A
Cycle time for CL=
-10 N/A
-12 N/A
26 SDRAM Access form Clock(3rd highest CAS latency) -8
N/A
tAC for CL=
-10 N/A
-12 N/A
27
Precharge to Active Minimum
-8 24ns
-10 30ns
-12 30ns
28
Row Active to Row Active Min.
-8 16ns
-10 20ns
-12 24ns
SPD DATA(hex)
80
08
04
0C
0A
01
40
00
01
80
A0
C0
60
80
80
00
80
04
00
01
0F
04
06
01
01
00
06
D0
E0
F0
70
80
90
00
00
00
00
00
00
18
1E
1E
10
14
18
MIT-DS-0127-0.0
MITSUBISHI
ELECTRIC
( 4 / 52 )
4. Mar.1997

4페이지










MH16S64AMA-8 전자부품, 판매, 대치품
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH16S64AMA provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command define basic commands
/WE
Command
CKE
A10
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0127-0.0
MITSUBISHI
ELECTRIC
( 7 / 52 )
4. Mar.1997

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