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부품번호 | MH16S64FFB-10L 기능 |
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기능 | 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM | ||
제조업체 | Mitsubishi | ||
로고 | |||
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64FFB is 16777216 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 16Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
-10,10L 100MHz
CLK Access Time
(Component SDRAM)
8.0ns(CL=3)
Utilizes industry standard 16M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
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ELECTRIC
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143
144
15. Jan.1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
19 CS# Latency
20 Write Latency
21 SDRAM Module Attributes
22 SDRAM Device Attributes:General
23 SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24 SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25 SDRAM Cycle time(3rd highest CAS latency)
26 SDRAM Access form Clock(3rd highest CAS latency)
27 Precharge to Active Minimum
28 Row Active to Row Active Min.
29 RAS to CAS Delay Min
30 Active to Precharge Min
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A9
1BANK
x64
0
LVTTL
10ns
8ns
Non-PARITY
self refresh(15.625uS)
x8
N/A
1
1/2/4/8/Full page
4bank
2/3
0
0
non-buffered,non-registered
Precharge All,Auto precharge
15ns
8ns
N/A
N/A
30ns
20ns
30ns
60ns
SPD DATA(hex)
80
08
04
0C
0A
01
40
00
01
A0
80
00
80
08
00
01
8F
04
06
01
01
00
0E
F0
80
00
00
1E
14
1E
3C
MIT-DS-0280-0.1
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ELECTRIC
( 4 / 55 )
15. Jan.1999
4페이지 Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH16S64FFB provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S0,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S0
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
define basic commands
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0280-0.1
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ELECTRIC
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15. Jan.1999
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
MH16S64FFB-10 | 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM | Mitsubishi |
MH16S64FFB-10L | 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM | Mitsubishi |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |