MH16S72BCFA-6 Datasheet PDF - Mitsubishi
| Part Number | MH16S72BCFA-6 | |
| Description | 1 /207 /959 /552-BIT ( 16 /777 /216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM | |
| Manufacturers | Mitsubishi | |
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MITSUBISHI LSIs
MH16S72BCFA-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
The MH16S72BCFA is 16777216 - word x 72-bit Synchronous
DRAM module. This consist of eighteen industry standard
16M x 4 Synchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package provides any
application where high densities and large of quantities memory
are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
Max.
Frequency
Access Time from CLK
[component level]
MH16S72BCFA-6
133MHz
5.4ns
(CL = 4 at Latch mode)
85pin
94pin
95pin
1pin
10pin
11pin
Utilizes industry standard 16M X 4 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in TSSOP
package,industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz
Fully synchronous operation referenced to clock rising edge
4-bank operation controlled by BA0,BA1(Bank Address)
/CAS latency -2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC133 specification.
APPLICATION
Main memory or graphic memory in computer systems
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-0310-0.0
MITSUBISHI
ELECTRIC
8/May. /1999
1
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MITSUBISHI LSIs
MH16S72BCFA-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH16S72BCFA provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge
option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
define basic commands
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0310-0.0
MITSUBISHI
ELECTRIC
8/May. /1999
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for MH16S72BCFA-6 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ MH16S72BCFA-6.PDF Datasheet ] | |
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