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MH16S72PJB-8 데이터시트 PDF




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부품번호 MH16S72PJB-8 기능
기능 1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
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MH16S72PJB-8 데이터시트, 핀배열, 회로
P rSepl iemci.n a r y
MITSUBISHI LSIs
MH16S72PJB-7, -8
1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
The MH16S72PJB is 16777216 - word x 72-bit
Synchronous DRAM module. This consist of nine industry
standard 16M x 8 Synchronous DRAMs in TSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
85pin 1pin
FEATURES
Type name
MH16S72PJB-7
MH16S72PJB-8
Max.
Frequency
100MHz
100MHz
CLK
Access Time
[component level]
6ns (CL = 2, 3)
6ns (CL = 3)
Utilizes industry standard 16M X 8 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in
TSSOP package and industry standard PLL in TSSOP
package
Single 3.3V +/- 0.3V supply
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC/100 specification.
(module Spec. Rev. 1.0 and SPD 1.2A)
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
APPLICATION
Main memory unit for computers, Microcomputer memory.
168pin 84pin
MIT-DS-0302-0.0
MITSUBISHI
ELECTRIC
11/Jan. /1999
1




MH16S72PJB-8 pdf, 반도체, 판매, 대치품
P rSepl iemci.n a r y
MITSUBISHI LSIs
MH16S72PJB-7, -8
1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
CK0
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0,2
/RAS,/CAS,/W
Input
Input
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/W defines basic commands.
A0-11
BA0-1
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-9.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Input
Bank Address:BA0,1 is not simply BA.BA0,1 specifies
the bank to which a command is applied.BA must be set
with ACT,PRE,READ,WRITE commands
Input/Output
Data In and Data out are referenced to the rising edge of
CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
Output
Register enable:When REGE is low,All control signals and
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
MIT-DS-0302-0.0
MITSUBISHI
ELECTRIC
11/Jan. /1999
4

4페이지










MH16S72PJB-8 전자부품, 판매, 대치품
P rSepl iemci.n a r y
MITSUBISHI LSIs
MH16S72PJB-7, -8
1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State
IDLE
ROW ACTIVE
READ
/S /RAS /CAS /WE Address
Command
Action
H X X XX
DESEL NOP
L H H HX
NOP
NOP
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT
Bank Active,Latch RA
L L H L BA,A10
PRE/PREA NOP*4
L L L HX
REFA
Auto-Refresh*5
Op-Code,
LLLL
Mode-Add
MRS
Mode Register Set*5
H X X XX
DESEL NOP
L H H HX
NOP
NOP
L H H L BA
TBST
NOP
Begin Read,Latch CA,
L H L H BA,CA,A10 READ/READA
Determine Auto-Precharge
WRITE/ Begin Write,Latch CA,
L H L L BA,CA,A10
WRITEA Determine Auto-Precharge
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA Precharge/Precharge All
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP(Continue Burst to END)
L H H HX
NOP
NOP(Continue Burst to END)
L H H L BA
TBST
Terminate Burst
Terminate Burst,Latch CA,
L H L H BA,CA,A10 READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
L H L L BA,CA,A10 WRITE/WRITEA Begin Write,Determine Auto-
Precharge*3
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA Terminate Burst,Precharge
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
MIT-DS-0302-0.0
MITSUBISHI
ELECTRIC
11/Jan. /1999
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
MH16S72PJB-7

1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Mitsubishi
Mitsubishi
MH16S72PJB-8

1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Mitsubishi
Mitsubishi

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