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MH16V645BWJ-6 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 MH16V645BWJ-6은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 MH16V645BWJ-6 기능
기능 HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
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MH16V645BWJ-6 데이터시트, 핀배열, 회로
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V645BWJ -5, -6
HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH16V645BWJ is 16777216-word x 64-bit dynamic
ram module. This consist of sixteen industry standard 16M
x 4 dynamic RAMs in SOJ and one industry standard
EEPROM in TSSOP.
The mounting of SOJs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
MH16V645BWJ-5 50 13 25 13 84 4.80
MH16V645BWJ-6 60 15 30 15 104 4.00
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs in SOJ and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
28.8mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH16V645BWJ -5 . . . . . . . . . . . . . . . . . . 5.76W(Max)
MH16V645BWJ -6 . . . . . . . . . . . . . . . . . . 5.19W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 16) decoupling capacitors
4096 refresh cycle every 64ms
Hyper-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
Gold plating contact pads
Row Address A0 ~ A12
Column Address A0 ~ A10
APPLICATION
Main memory unit for computers , Microcomputer memory
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
168pin 84pin
MIT-DS-0240-0.0
MITSUBISHI
ELECTRIC
( 1 / 22 )
28/Jul/`98




MH16V645BWJ-6 pdf, 반도체, 판매, 대치품
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V645BWJ -5, -6
HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
FUNCTION
The MH16V645BWJ provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Hyper page mode,
/CAS before /RAS refresh, and delayed-write. The
input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
Hidden refresh
/CAS before /RAS refresh
Standby
/RAS
ACT
ACT
ACT
ACT
ACT
ACT
NAC
/CAS
ACT
ACT
ACT
ACT
ACT
ACT
DNC
Inputs
/W /OE
NAC ACT
ACT DNC
ACT DNC
ACT
DNC
NAC
ACT
ACT
DNC
DNC DNC
adRdorwess
Column
address
APD APD
APD APD
APD APD
APD APD
DNC DNC
DNC DNC
DNC DNC
Input/Output Refresh
Input Output
OPN
VLD
VLD
OPN
YES
YES
VLD IVD YES
VLD
OPN
DNC
VLD
VLD
OPN
YES
YES
YES
DNC OPN NO
Remark
Hyper page
mode
identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
MIT-DS-0240-0.0
MITSUBISHI
ELECTRIC
( 4 / 22 )
28/Jul/`98

4페이지










MH16V645BWJ-6 전자부품, 판매, 대치품
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V645BWJ -5, -6
HYPER PAGE MODE 1073741824 - BIT ( 16777216 - WORD BY 64 - BIT ) DYNAMIC RAM
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS /RAS low pulse width
tCAS /CAS low pulse width
tCSH
tRSH
/CAS hold time after /RAS low
/RAS hold time after /CAS low
tRCS Read Setup time after /CAS high
tRCH Read hold time after /CAS low
tRRH Read hold time after /RAS low
tRAL Column address to /RAS hold time
tCAL Column address to /CAS hold time
tORH /RAS hold time after /OE low
tOCH /CAS hold time after /OE low
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
(Note 22)
(Note 22)
Limits
-5 -6
Min Max Min Max
84 104
50 10000
60 10000
8 10000
10 10000
35 48
13 15
00
00
00
25 30
13 18
13 15
13 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Write setup time before /CAS low
(Note 24)
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
Limits
-5 -6
Min Max Min
Max
84 104
50 10000
60 10000
8 10000
10 10000
35 40
13 15
00
8 10
8 10
8 10
8 10
00
8 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/OE hold time after /W low
(Note23)
(Note24)
(Note24)
(Note24)
Limits
-5 -6
Min Max Min Max
109 133
75 10000
89 10000
38 10000
44 10000
70 82
38 44
00
28 32
65 77
40 47
13 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD (min), tAWDtAWD(min) and tCPWD tCPWD(min) (for Hyper page mode cycle only),
the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access
time and until /CAS or /OE goes back to VIH) is indeterminate.
MIT-DS-0240-0.0
MITSUBISHI
ELECTRIC
( 7 / 22 )
28/Jul/`98

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