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MH16V725BATJ-5 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 MH16V725BATJ-5은 전자 산업 및 응용 분야에서
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부품번호 MH16V725BATJ-5 기능
기능 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
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MH16V725BATJ-5 데이터시트, 핀배열, 회로
Preliminary Spec.
MITSUBISHI LSIs
MH16V725BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH16V725BATJ is 16777216-word x 72-bit dynamic
ram module. This consist of eighteen industry standard 16M
x 4 dynamic RAMs in TSOP and three industry standard input
buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
MH16V725BATJ-5
MH16V725BATJ-6
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
50 18 30 18 84 5.50
60 20 35 20 104 4.60
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual in-line pacege)
Single 3.3V(+/-0.3V) supply operation
Low stand-by power dissipation . . . . . . . . 121mW(Max)
Low operation power dissipation
MH16V725BATJ -5 . . . . . . . . . . . . . . . . . 6.58W(Max)
MH16V725BATJ -6 . . . . . . . . . . . . . . . . . 5.94W(Max)
All input,output LVTTL compatible
Includes(0.22uF x 20) decoupling capacitors
4096 refresh cycle every 64ms (A0~A12)
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
APPLICATION
Main memory unit for computers , Microcomputer memory
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1
-5 1 1 1 1 1 0 0 0 0 0
-6 1 1 1 1 1 1 1 0 0 0
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
MIT-DS-0271-0.0
MITSUBISHI
ELECTRIC
( 1 / 22 )
168pin 84pin
Oct.1.1998




MH16V725BATJ-5 pdf, 반도체, 판매, 대치품
Preliminary Spec.
MITSUBISHI LSIs
MH16V725BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
FUNCTION
The MH16V725BATJ provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Hyper page mode, /CAS
before /RAS refresh, and delayed-write. The input conditions
for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
Hidden refresh
/CAS before /RAS refresh
Standby
/RAS
ACT
ACT
ACT
ACT
ACT
ACT
NAC
/CAS
ACT
ACT
ACT
ACT
ACT
ACT
DNC
Inputs
/W /OE
NAC
ACT
ACT
ACT
ACT
DNC
DNC
ACT
DNC
NAC
ACT
DNC
DNC DNC
Row Column
address address
APD APD
APD APD
APD APD
APD APD
DNC DNC
DNC DNC
DNC DNC
Input/Output
Refresh
Input Output
OPN VLD NO
VLD OPN NO
VLD IVD NO
VLD VLD NO
OPN VLD YES
DNC OPN YES
DNC OPN NO
Remark
Hyper page
mode
identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
MIT-DS-0271-0.0
MITSUBISHI
ELECTRIC
( 4 / 22 )
Oct.1.1998

4페이지










MH16V725BATJ-5 전자부품, 판매, 대치품
Preliminary Spec.
MITSUBISHI LSIs
MH16V725BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS /RAS iow pulse width
tCAS /CAS iow pulse width
tCSH /CAS hold time after /RAS iow
tRSH /RAS hold time after /CAS iow
tRCS Read Setup time after /CAS high
tRCH Read hold time after /CAS iow
(Note 22)
tRRH Read hold time after /RAS iow
(Note 22)
tRAL Column address to /RAS hold time
tCAL Column address to /CAS hold time
tORH /RAS hold time after /OE iow
tOCH /CAS hold time after /OE iow
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Limits
-5 -6
Min Max Min Max
84 104
50 10000 60 10000
8 10000 10 10000
30 43
18 20
00
00
00
30 35
13 18
18 20
13 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Write cycle time
/RAS iow pulse width
/CAS iow pulse width
/CAS hold time after /RAS iow
/RAS hold time after /CAS iow
Write setup time before /CAS low
Write hold time after /CAS iow
/CAS hold time after /W iow
/RAS hold time after W iow
Write pulse width
Data setup time before /CAS iow or W iow
Data hold time after /CAS iow or W iow
(Note 24)
Limits
-5 -6
Min Max Min Max
84 104
50 10000 60 10000
8 10000 10 10000
30 35
18 20
00
8 10
8 10
13 15
8 10
-5 -5
13 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read-Write and Read-Modify-Write Cycles
Limits
Symbol
Parameter
tRWC Read write/read modify write cycle time
(Note23)
-5
Min Max
109
-6
Min Max
133
Unit
ns
tRAS RAS iow pulse width
75 10000 89 10000 ns
tCAS CAS iow pulse width
38 10000 44 10000 ns
tCSH CAS hold time after RAS low
65 77
ns
tRSH
tRCS
tCWD
tRWD
tAWD
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS iow to W iow
Delay time, RAS iow to W iow
Delay time, address to W iow
(Note24)
(Note24)
(Note24)
43
0
28
60
40
49
0
32
72
47
ns
ns
ns
ns
ns
tOEH OE hold time after W iow
13 15
ns
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24: tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle
and the DQ pins will remain high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD (min), tAWDtAWD(min)
and tCPWDtCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the
data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE
goes back to VIH) is indeteminate.
MIT-DS-0271-0.0
MITSUBISHI
ELECTRIC
( 7 / 22 )
Oct.1.1998

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