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PDF MH1M365CNXJ-7 Data sheet ( Hoja de datos )
| Número de pieza | MH1M365CNXJ-7 | |
| Descripción | HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
DESCRIPTION
The MH1M365CXJ/CNXJ is 1048576-word x 36-bits dynamic
RAM. This consists of two industry standard 1M x 16 dynamic
RAMs in SOJ and one industry 1M x 4 dyanmic RAMs in SOJ.
The mounting of SOJ on a single in-line package provides any
application where high densities and large quantities of memory
are required. This is a socket-type memory module,suitable for
easy interchange or addition of modules.
FEATURES
Type name
RAS
CAS Address Cycle Power
access access access
dissipa-
time
time time
time tion
(max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
MH1M365CXJ/CNXJ-5 50 13 25
90 2120
MH1M365CXJ/CNXJ-6 60 15 30 110 1750
MH1M365CXJ/CNXJ-7 70 20 35 130 1520
72pin single in-line package
Single 5.0V ± 10% supply
Low stand-by power dissipation
16.5mW (Max)
Low operating power dissipation
MH1M365CXJ/CNXJ- 5
MH1M365CXJ/CNXJ- 6
MH1M365CXJ/CNXJ- 7
CMOS lnput level
2.67W (Max)
2.20W (Max)
1.90W (Max)
Hyper-page mode , RAS-only refresh , CAS before RAS
refresh, Hidden refresh capabilities
All inputs and output directly TTL compatible
1024 refresh cycles every 16.4ms (A0 ~ A9)
MH1M365CXJ
MH1M365CNXJ
Gold plating
Nickel+solder plating
APPLICATION
Main memory unit for computers, Microcomputer memory,
Refresh memory for CRT
PIN CONFIGURATION (TOP VIEW)
[Single side]
1.Vss
2.DQ0
3.DQ16
4.DQ1
5.DQ17
6.DQ2
7.DQ18
8.DQ3
11.NC
10.Vcc
11.NC
12.A0
13.A1
14.A2
15.A3
16.A4
17.A5
18.A6
37.MP1 1
2
38.MP3 3
4
39.Vss 5
6
40.CAS0
7
8
41.CAS2
9
10
42.CAS3
11
12
13
43.CAS1 14
15
44.RAS0 16
17
45.NC 18
19
46.NC
20
21
47.W
22
23
48.NC
24
25
26
49.DQ8 27
28
50.DQ24 29
30
51.DQ9
31
32
52.DQ25
33
34
53.DQ10
35
36
54.DQ26
19.NC 55.DQ11
20.DQ4
56.DQ27
37
38
21.DQ20
57.DQ12
39
40
22.DQ5
58.DQ28
41
42
23.DQ21 59.Vcc
43
44
45
24.DQ6 60.DQ29 46
47
25.DQ22 61.DQ13 48
49
26.DQ7 62.DQ30 50
51
27.DQ23
63.DQ14
52
53
28.A7
64.DQ31
54
55
29.NC
65.DQ15
56
57
58
30.Vcc 66.NC 59
60
31.A8 67.PD1 61
62
32.A9
68.PD2
63
64
33.NC
69.PD3
65
66
34.RAS2 70.PD4
67
68
35.MP2 71.NC
69
70
71
36.MP0 72.Vss 72
-5 -6 -7
PD1 Vss Vss Vss
PD2 Vss Vss Vss
PD3 Vss NC Vss
PD4 Vss NC NC
Outline 72N9K-C
NC: NO CONNECTION
MIT-DS-0084-1.0
MITSUBISHI
ELECTRIC
( 1 / 15 )
Oct.15.96
1 page  
MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0 ~ 70°C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted See notes 14,15)
Symbol
Parameter
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tRDD
tCDD
tT
Refresh cycle time
RAS high pulse width
Delay time, RAS low to CAS low
(Note16)
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
(Note17)
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
(Note18)
Column address hold time after CAS low
Delay time, data to CAS low
(Note19)
Delay time, RAS high to data
(Note20)
Delay time, CAS high to data
(Note20)
Transition time
(Note21)
MH1M365C -5
Min Max
16.4
30
18 37
5
0
8
13 25
0
0 10
8
8
0
13
13
1 50
Limits
MH1M365C -6
Min Max
16.4
40
20 45
5
0
10
15 30
0
0 13
10
10
0
15
15
1 50
MH1M365C -7
Min Max
16.4
50
20 50
5
0
10
15 35
0
0 13
10
10
0
20
20
1 50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 14: The timing requirements are assumed tT =3ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA.
17: tRAD(max) is specified as a reference point only. If tRAD ≤ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
19: tDZC must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tCAL
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read Setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
Column address to CAS hold time
(Note 22)
(Note 22)
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
MH1M365C -5
Min Max
90
50 10000
8 10000
40
13
0
0
10
25
13
Limits
MH1M365C -6
Min
110
Max
60 10000
10 10000
48
15
0
0
10
30
18
MH1M365C -7
Min Max
130
70 10000
13 10000
55
20
0
0
10
35
23
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIT-DS-0084-1.0
MITSUBISHI
ELECTRIC
( 5 / 15 )
Oct.15.96
5 Page 
MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
RAS
VIH
VIL
CAS
VIH
VIL
A0~A9
VIH
VIL
VIH
W
VIL
DQ(INPUTS)
VIH
VIL
VOH
DQ(OUTPUTS)
VOL
tRAS
tRP
tCRP
tCSH
tHPC
tRSH
tRCD
tCAS
tCP tCAS
tCP
tCAS
tCRP
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN-1
tRCS
tASC tCAH
COLUMN-2
tRCH
tCPRH
tASC tCAH
COLUMN-3
tRAL
tRCS
tASR
ROW
ADDRESS
tRRH
tRCH
tDZC
tWPE
tCAC
tAA
tCLZ
Hi-Z
tRAC
Hi-Z
tCAC
tAA
tDOH
tCAC
tAA
tWEZ tCLZ
DATA
VALID-1
tCPA
DATA
VALID-2
Hi-Z
tCPA
tRDD
tCDD
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
MIT-DS-0084-1.0
MITSUBISHI
ELECTRIC
(11 / 15 )
Oct.15.96
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MH1M365CNXJ-7.PDF ] | |
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