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MH1M365CXJ-6 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 MH1M365CXJ-6은 전자 산업 및 응용 분야에서
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부품번호 MH1M365CXJ-6 기능
기능 HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
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MH1M365CXJ-6 데이터시트, 핀배열, 회로
MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
DESCRIPTION
The MH1M365CXJ/CNXJ is 1048576-word x 36-bits dynamic
RAM. This consists of two industry standard 1M x 16 dynamic
RAMs in SOJ and one industry 1M x 4 dyanmic RAMs in SOJ.
The mounting of SOJ on a single in-line package provides any
application where high densities and large quantities of memory
are required. This is a socket-type memory module,suitable for
easy interchange or addition of modules.
FEATURES
Type name
RAS
CAS Address Cycle Power
access access access
dissipa-
time
time time
time tion
(max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
MH1M365CXJ/CNXJ-5 50 13 25
90 2120
MH1M365CXJ/CNXJ-6 60 15 30 110 1750
MH1M365CXJ/CNXJ-7 70 20 35 130 1520
72pin single in-line package
Single 5.0V ± 10% supply
Low stand-by power dissipation
16.5mW (Max)
Low operating power dissipation
MH1M365CXJ/CNXJ- 5
MH1M365CXJ/CNXJ- 6
MH1M365CXJ/CNXJ- 7
CMOS lnput level
2.67W (Max)
2.20W (Max)
1.90W (Max)
Hyper-page mode , RAS-only refresh , CAS before RAS
refresh, Hidden refresh capabilities
All inputs and output directly TTL compatible
1024 refresh cycles every 16.4ms (A0 ~ A9)
MH1M365CXJ
MH1M365CNXJ
Gold plating
Nickel+solder plating
APPLICATION
Main memory unit for computers, Microcomputer memory,
Refresh memory for CRT
PIN CONFIGURATION (TOP VIEW)
[Single side]
1.Vss
2.DQ0
3.DQ16
4.DQ1
5.DQ17
6.DQ2
7.DQ18
8.DQ3
11.NC
10.Vcc
11.NC
12.A0
13.A1
14.A2
15.A3
16.A4
17.A5
18.A6
37.MP1 1
2
38.MP3 3
4
39.Vss 5
6
40.CAS0
7
8
41.CAS2
9
10
42.CAS3
11
12
13
43.CAS1 14
15
44.RAS0 16
17
45.NC 18
19
46.NC
20
21
47.W
22
23
48.NC
24
25
26
49.DQ8 27
28
50.DQ24 29
30
51.DQ9
31
32
52.DQ25
33
34
53.DQ10
35
36
54.DQ26
19.NC 55.DQ11
20.DQ4
56.DQ27
37
38
21.DQ20
57.DQ12
39
40
22.DQ5
58.DQ28
41
42
23.DQ21 59.Vcc
43
44
45
24.DQ6 60.DQ29 46
47
25.DQ22 61.DQ13 48
49
26.DQ7 62.DQ30 50
51
27.DQ23
63.DQ14
52
53
28.A7
64.DQ31
54
55
29.NC
65.DQ15
56
57
58
30.Vcc 66.NC 59
60
31.A8 67.PD1 61
62
32.A9
68.PD2
63
64
33.NC
69.PD3
65
66
34.RAS2 70.PD4
67
68
35.MP2 71.NC
69
70
71
36.MP0 72.Vss 72
-5 -6 -7
PD1 Vss Vss Vss
PD2 Vss Vss Vss
PD3 Vss NC Vss
PD4 Vss NC NC
Outline 72N9K-C
NC: NO CONNECTION
MIT-DS-0084-1.0
MITSUBISHI
ELECTRIC
( 1 / 15 )
Oct.15.96




MH1M365CXJ-6 pdf, 반도체, 판매, 대치품
MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
CAPACITANCE (Ta=0 ~ 70 °C, Vcc=5.0V ± 10%, Vss=0V, unless otherwise noted)
Symbol
Parameter
Test conditions
CI (A)
CI (W)
CI (RAS)
CI (CAS)
CI / O
Input capacitance,address inputs
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports
VI=Vss
f=1MHZ
Vi=25mVrms
Limits
Min Typ Max
30
36
36
29
22
Unit
pF
pF
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0 ~ 70 °C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted , see notes 6,14,15)
Symbol
Parameter
tCAC
tRAC
tAA
tCPA
tOHC
tOHR
tCLZ
tWEZ
tOFF
tREZ
Access time from CAS
(Note 7,8)
Access time from RAS
(Note 7,9)
Column address access time
(Note 7,10)
Access time from CAS precharge
(Note 7,11)
Output hold time from CAS
Output hold time from RAS
(Note 13)
Output low impedance time from CAS low (Note 7)
Output disable time after WE high
(Note 12)
Output disable time after CAS high
(Note 12,13)
Output disable time after RAS high
(Note 12,13)
MH1M365C -5
Min Max
13
50
25
30
5
5
5
13
13
13
Limits
MH1M365C -6
Min Max
15
60
30
35
5
5
5
15
15
15
MH1M365C -7
Min Max
20
70
35
40
5
5
5
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a RAS clock such as RAS-Only refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 16.4 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-5mA) / VOL=0.4V(IOL=-4.2mA) load 100pF.
The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL).
8: Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP t CP(max).
9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD tRAD(max) and tASC tASC(max).
11: Assumes that tCP tCP(max) and tASC tASC(max).
12: tWEZ(max) ,tOFF(max) and tREZ(max)defines the time at which the output achieves the high impedance state ( IOUT I ± 10 µA I)
and is not reference to VOH(min) or VOL(max).
13: Output is disabled after both RAS and CAS go to high.
MIT-DS-0084-1.0
MITSUBISHI
ELECTRIC
( 4 / 15 )
Oct.15.96

4페이지










MH1M365CXJ-6 전자부품, 판매, 대치품
MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
Timing Diagrams (Note 27)
Read Cycle
RAS
VIH
VIL
CAS
VIH
VIL
A0~A9
VIH
VIL
VIH
W
VIL
DQ(INPUTS)
VIH
VIL
VOH
DQ(OUTPUTS)
VOL
tRC
tRAS
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tRAD
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRAL
tCAL
tRCS
tRP
tCRP
tASR
ROW
ADDRESS
tRRH
tRCH
tDZC
Hi-Z
tRAC
tCAC
tAA
tCLZ
Hi-Z
tRDD
tCDD
tREZ
tOHR
tWEZ
tOFF
tOHC
DATA VALID
Hi-Z
MIT-DS-0084-1.0
Note 27
Indicates the don't care input.
VIH(min) VIN VIH(max) or
VIL(min) VIN VIL(max)
Indicates the invalid output.
MITSUBISHI
ELECTRIC
( 7 / 15 )
Oct.15.96

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HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM

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MH1M365CXJ-6

HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM

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