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MH1S64CWXTJ-15 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 MH1S64CWXTJ-15은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 MH1S64CWXTJ-15 기능
기능 67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
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MH1S64CWXTJ-15 데이터시트, 핀배열, 회로
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH1S64CWXTJ-12,-15,-1539
67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH1S64CWXTJ is 1048576-word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 1Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-12 83MHz
8ns(CL=3)
85pin 1pin
94pin
95pin
10pin
11pin
-15
67MHz
9.5ns (CL=2)
-1539
67MHz
9ns (CL=3)
Utilizes industry standard 1M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
124pin 40pin
125pin 41pin
Clock frequency 83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
168pin 84pin
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
SPD table
Byte No.
MH1S64CWXTJ-12
MH1S64CWXTJ-15
MH1S64CWXTJ-1539
MIT-DS-0064-0.2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 126 127
80 08 04 0C 08 01 40 00 01 C0 80 00 80 00 06 01 05 02 06 01 01 83 06
80 08 04 0C 08 01 40 00 01 F0 95 00 80 00 06 01 05 02 06 01 01 66 06
80 08 04 0C 08 01 40 00 01 F0 90 00 80 00 04 01 05 02 04 01 01 66 04
MITSUBISHI
ELECTRIC
Oct.28.1996
( 1 / 45 )




MH1S64CWXTJ-15 pdf, 반도체, 판매, 대치품
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH1S64CWXTJ-12,-15,-1539
67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
CK
(CK0)
CKE
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S
(/S0 &/S2)
/RAS,/CAS,/WE
Input
Input
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/WE defines basic commands.
A0-10
BA
DQ0-63
DQMB0-7
Vdd,Vss
Input
A0-10 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-10.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Input
Bank Address:BA is not simply BA.BA specifies the bank
to which a command is applied.BA must be set with
ACT,PRE,READ,WRITE commands
Input/Output
Data In and Data out are referenced to the rising edge of
CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
SLA Input Serial clock for serial PD
SDA
Output Serial data for serial PD
MIT-DS-0064-0.2
MITSUBISHI
ELECTRIC
( 4 / 45 )
Oct.28.1996

4페이지










MH1S64CWXTJ-15 전자부품, 판매, 대치품
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH1S64CWXTJ-12,-15,-1539
67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Current State
IDLE
ROW ACTIVE
READ
/S /RAS /CAS /WE Address
Command
Action
H X X XX
DESEL NOP
L H H HX
NOP
NOP
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT
Bank Active,Latch RA
L L H L BA,A10
PRE/PREA NOP*4
L L L HX
REFA
Auto-Refresh*5
Op-Code,
LLLL
Mode-Add
MRS
Mode Register Set*5
H X X XX
DESEL NOP
L H H HX
NOP
NOP
L H H L BA
TBST
NOP
Begin Read,Latch CA,
L H L H BA,CA,A10 READ/READA
Determine Auto-Precharge
WRITE/ Begin Write,Latch CA,
L H L L BA,CA,A10
WRITEA Determine Auto-Precharge
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA Precharge/Precharge All
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP(Continue Burst to END)
L H H HX
NOP
NOP(Continue Burst to END)
L H H L BA
TBST
Terminate Burst
Terminate Burst,Latch CA,
L H L H BA,CA,A10 READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
L H L L BA,CA,A10 WRITE/WRITEA Begin Write,Determine Auto-
Precharge*3
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA Terminate Burst,Precharge
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
MIT-DS-0064-0.2
MITSUBISHI
ELECTRIC
( 7 / 45 )
Oct.28.1996

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