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PDF MH1S64CWXTJ-1539 Data sheet ( Hoja de datos )
| Número de pieza | MH1S64CWXTJ-1539 | |
| Descripción | 67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH1S64CWXTJ-12,-15,-1539
67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH1S64CWXTJ is 1048576-word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 1Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-12 83MHz
8ns(CL=3)
85pin 1pin
94pin
95pin
10pin
11pin
-15
67MHz
9.5ns (CL=2)
-1539
67MHz
9ns (CL=3)
Utilizes industry standard 1M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
124pin 40pin
125pin 41pin
Clock frequency 83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
168pin 84pin
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
SPD table
Byte No.
MH1S64CWXTJ-12
MH1S64CWXTJ-15
MH1S64CWXTJ-1539
MIT-DS-0064-0.2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 126 127
80 08 04 0C 08 01 40 00 01 C0 80 00 80 00 06 01 05 02 06 01 01 83 06
80 08 04 0C 08 01 40 00 01 F0 95 00 80 00 06 01 05 02 06 01 01 66 06
80 08 04 0C 08 01 40 00 01 F0 90 00 80 00 04 01 05 02 04 01 01 66 04
MITSUBISHI
ELECTRIC
Oct.28.1996
( 1 / 45 )
1 page  
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH1S64CWXTJ-12,-15,-1539
67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH1S64CWXTJ provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command define basic commands
/WE
Command
CKE
A10
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0064-0.2
MITSUBISHI
ELECTRIC
( 5 / 45 )
Oct.28.1996
5 Page 
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH1S64CWXTJ-12,-15,-1539
67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
CK CK
Current State n-1 n
SELF -
HX
REFRESH*1 L H
LH
LH
LH
LH
LL
POWER
DOWN
HX
LH
LL
ALL BANKS H H
IDLE*2
HL
HL
HL
HL
HL
HL
LX
ANY STATE H H
other than
HL
listed above L H
LL
/S /RAS /CAS /WE Add
Action
X X X X X INVALID
H X X X X Exit Self-Refresh(Idle after tRC)
L H H H X Exit Self-Refresh(Idle after tRC)
L H H L X ILLEGAL
L H L X X ILLEGAL
L L X X X ILLEGAL
X X X X X NOP(Maintain Self-Refresh)
X X X X X INVALID
X X X X X Exit Power Down to Idle
X X X X X NOP(Maintain Self-Refresh)
X X X X X Refer to Function Truth Table
L L L H X Enter Self-Refresh
H X X X X Enter Power Down
L H H H X Enter Power Down
L H H L X ILLEGAL
L H L X X ILLEGAL
L L X X X ILLEGAL
X X X X X Refer to Current State = Power Down
X X X X X Refer to Function Truth Table
X X X X X Begin CK0 Suspend at Next Cycle*3
X X X X X Exit CK0 Suspend at Next Cycle*3
X X X X X Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0064-0.2
MITSUBISHI
ELECTRIC
( 11 / 45 )
Oct.28.1996
11 Page | ||
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