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MH1S72CPG-15 데이터시트 PDF




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부품번호 MH1S72CPG-15 기능
기능 75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
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MH1S72CPG-15 데이터시트, 핀배열, 회로
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
DESCRIPTION
The MH1S72CPG is 1048576-word by 64-bit
Synchronous DRAM module. This consists of five
industry standard 1Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-10 100MHz
8ns(CL=3)
85pin 1pin
94pin
95pin
10pin
11pin
-12 83MHz
8ns (CL=3)
-15 67MHz
9ns (CL=3)
Utilizes industry standard 1M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
124pin 40pin
125pin 41pin
Clock frequency 100MHz/83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
168pin 84pin
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
Module item "-10","-12" , and "-15" show mounted SDRAM devices Cycle time(min.).
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 1 / 47 )
28.Mar.1997




MH1S72CPG-15 pdf, 반도체, 판매, 대치품
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
Serial Presence Detect Table
Byte
Function described
0 Defines # bytes written into serial memory at module mfgr
1 Total # bytes of SPD memory device
2 Fundamental memory type
3 # Row Addresses on this assembly
4 # Column Addresses on this assembly
5 # Module Banks on this assembly
6 Data Width of this assembly...
7 ... Data Width continuation
8 Voltage interface standard of this assembly
9 SDRAM Cycletime at Max. Supported CAS Latency (CL). -10
Cycle time for CL=3
-12
-15
10
SDRAM Access from Clock
-10
tAC for CL=3
-12
-15
11 DIMM Configuration type (Non-parity,Parity,ECC)
12 Refresh Rate/Type
13 SDRAM width,Primary DRAM
14 Error Checking SDRAM data width
15 Minimum Clock Delay,Back to Back Random Column Addresses
16 Burst Lengths Supported
17 # Banks on Each SDRAM device
18 CAS# Latency
19 CS# Latency
20 Write Latency
21 SDRAM Module Attributes
22 SDRAM Device Attributes:General
23
SDRAM Cycle time(2nd highest CAS latency)
-10
Cycle time for CL=2
-12
-15
24 SDRAM Access form Clock(2nd highest CAS latency) -10
tAC for CL=2
-12
-15
25
SDRAM Cycle time(3rd highest CAS latency)
-10
Cycle time for CL=1
-12
-15
26 SDRAM Access form Clock(3rd highest CAS latency) -10
tAC for CL=1
-12
-15
27
Precharge to Active Minimum
-10
-12
-15
28
Row Active to Row Active Min.
-10
-12
-15
SPD enrty data
128
256 Bytes
SDRAM
A0-A10
A0-A7
1BANK
x72
0
LVTTL
10ns
12ns
15ns
8ns
8ns
9ns
ECC
self refresh(15.625uS)
x16
x8
1
1/2/4/8
2bank
CL=1/2/3
0
0
non-buffered,non-registered
Precharge All,Auto precharge
15ns
15ns
20ns
9ns
9.5ns
12ns
30ns
30ns
30ns
27ns
27ns
30ns
30ns
30ns
40ns
20ns
24ns
30ns
SPD DATA(hex)
80
08
04
0B
08
01
48
00
01
A0
C0
F0
80
80
90
02
80
10
08
01
0F
02
06
01
01
00
06
F0
F0
FF
90
95
C0
78
78
78
6C
6C
78
1E
1E
28
14
18
1E
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 4 / 47 )
28.Mar.1997

4페이지










MH1S72CPG-15 전자부품, 판매, 대치품
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH1S72CPG provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command define basic commands
/WE
Command
CKE
A10
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 7 / 47 )
28.Mar.1997

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