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MH1V36CAM-7 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 MH1V36CAM-7은 전자 산업 및 응용 분야에서
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부품번호 MH1V36CAM-7 기능
기능 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
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MH1V36CAM-7 데이터시트, 핀배열, 회로
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH1V36CAM-6,-7
FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
DESCRIPTION
The MH1V36CAM is an 1M word by 36-bit dynamic
RAM module and consists of 2 industry standard
1M X 16 dynamic RAMs in TSOP and 1 industry
standard 1M X 4(4CAS) dynamic RAMs in TSOP.
The ICs are mounted on both sides of one small
ceracom PC board with flash gold plating and form a
convenient 68-pin package.
FEATURES
Type name
MH1V36CAM-6
RAS
CAS Address OE
Cycle
access access access access
time
time
time
time
time
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
60 15 30 15 110
MH1V36CAM-7
70 20 35
20 130
Utilizes industry standard 1M X 16 DRAMs in TSOP package
and industry standard 1M X 4(4CAS) DRAM in TSOP
package
Single 3.3V +/- 0.3V supply
Low stand-by power dissipation
9mW (Max) . . . . . . . . . . . . . . . . . CMOS lnput level
Low operating power dissipation
MH1V36CAM - 6 . . . . . . . . . . . . . . . . 1.37W (Max)
MH1V36CAM - 7 . . . . . . . . . . . . . . . . 1.20W (Max)
All inputs, output TTL compatible and low capacitance
1024 refresh cycles every 16.4ms (A0 ~ A9)
Includes 2pcs 0.22uF decoupling capacitors
APPLICATION
Main memory unit for computers, Microcomputer memory,
Refresh memory for CRT
PIN CONFIGURATION ( TOP VIEW )
DQ1 1
DQ2 2
DQ3 3
DQ4 4
DQ5 5
Vss 6
DQ6 7
DQ7 8
DQ8 9
DQP1 10
DQ9 11
Vcc 12
DQ10 13
DQ11 14
DQ12 15
DQ13 16
DQ14 17
Vss 18
DQ15 19
DQ16 20
DQP2 21
Vcc 22
/CAS0 23
/CAS3 24
A0 25
A1 26
A2 27
Vss 28
A3 29
A4 30
A5 31
/RAS 32
A6 33
Vcc 34
68 DQP4
67 DQ32
66 DQ31
65 DQ30
64 DQ29
63 Vss
62 DQ28
61 DQ27
60 DQ26
59 DQ25
58 DQP3
57 Vcc
56 DQ24
55 DQ23
54 DQ22
53 DQ21
52 DQ20
51 Vss
50 DQ19
49 DQ18
48 DQ17
47 Vcc
46 /CAS2
45 /CAS1
44 /W
43 /OE
42 RFU(NC)
41 Vss
40 RFU(NC)
39 RFU(NC)
38 A9
37 A8
36 A7
35 Vcc
MIT-DS-0027-0.0
MITSUBISHI
ELECTRIC
( 1 / 18 )
21 May 1996




MH1V36CAM-7 pdf, 반도체, 판매, 대치품
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH1V36CAM-6,-7
FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
SWITCHING CHARACTERISTICS (Ta=0~70°C , Vcc=3.3V +/-0.3V, Vss=0V, unless otherwise noted , see notes 5,12,13)
Symbol
Parameter
tCAC Access time from CAS
(Note 6,7)
tRAC Access time from RAS
(Note 6,8)
tAA Columu address access time
(Note 6,9)
tCPA Access time from CAS precharge
(Note 6,10)
tOEA Access time from OE
(Note 6)
tCLZ Output low impedance time from CAS low (Note 6)
tOFF Output disable time after CAS high
(Note 11)
tOEZ Output disable time after OE high
(Note 11)
Limits
-6 -7
Min Max
Min Max
15 20
60 70
30 35
35 40
15 20
55
0 15 0 20
0 15 0 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Note 5: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a RAS clock such as RAS-Only refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 16.4 ms) of RAS inactivity before proper device operation is achieved.
6: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) load 100pF.
The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL).
7: Assumes that tRCDÅDtRCD(max) and tASC tASC(max).
8: Assumes that tRCD tRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
9: Assumes that tRAD tRAD(max) and tASCtASC(max).
10: Assumes that tCP tCP(max) and tASCtASC(max).
11: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT I +/- 10uAI) and is not reference to
VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 °C, Vcc=3.3V +/- 0.3V, Vss=0V, unless otherwise noted See notes 12,13)
Symbol
Parameter
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Refresh cycle time
RAS high pulse width
Delay time, RAS low to CAS low
(Note14)
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
(Note15)
Row address setup time before RAS low
Column address setup time before CAS low (Note16)
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
(Note17)
Delay time, data to OE low
(Note17)
Delay time, CAS high to data
(Note18)
Delay time, OE high to data
(Note18)
Transition time
(Note19)
Limits
-6 -7
Min Max
Min
16.4
40 50
20 45 20
10 10
00
10 10
15 30 15
00
0 10
0
10 10
15 15
00
00
15 20
15 20
1 50 1
Max
16.4
50
35
10
50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 12: The timing requirements are assumed tT =5ns.
13: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
14: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min).
15: tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA.
16: tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC.
17: Either tDZC or tDZO must be satisfied.
18: Either tCDD or tODD must be satisfied.
19: tT is measured between VIH(min) and VIL(max).
MIT-DS-0027-0.0
MITSUBISHI
ELECTRIC
( 4 / 18 )
21 May 1996

4페이지










MH1V36CAM-7 전자부품, 판매, 대치품
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH1V36CAM-6,-7
FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
Timing Diagrams (Note 27)
Read Cycle
tRC
tRAS
RAS
VIH
VIL
CAS
VIH
VIL
A0 ~ A9
VIH
VIL
tCRP
tRCD
tCSH
tRSH
tCAS
tRAD
tASR tRAH
ROW
ADDRESS
tASC
tRAL
tCAH
COLUMN
ADDRESS
VIH
W
VIL
tRCS
tDZC
tRP
tRPC tCRP
tCPN
tRCH
tASR
tRRH
ROW
ADDRESS
tCDD
DQ VIH
(INPUTS) VIL
DQ VOH
(OUTPUTS) VOL
VIH
OE
VIL
tCAC
tAA
tCLZ
Hi-Z
tRAC
tDZO
Hi-Z
tOFF
DATA VALID
tOEZ
tOEA
tOCH
tODD
Hi-Z
tORH
MIT-DS-0027-0.0
Note 27
Indicates the don't care input.
VIH(min)VINVIH(max) or VIL(min)VINVIL(max)
Indicates the invalid output.
Indicates the skew of the four inputs.
MITSUBISHI
ELECTRIC
( 7 / 18 )
21 May 1996

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