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기능 EPROM Memory Programming Specification
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PIC12C672 데이터시트, 핀배열, 회로
PIC12C67X AND PIC12CE67X
EPROM Memory Programming Specification
This document includes the programming
specifications for the following devices:
• PIC12C671
• PIC12C672
• PIC12CE673
• PIC12CE674
1.0 PROGRAMMING THE
PIC12C67X AND PIC12CE67X
The PIC12C67X and PIC12CE67X can be pro-
grammed using a serial method. In serial mode the
PIC12C67X and PIC12CE67X can be programmed
while in the users system. This allows for increased
design flexibility.
1.1 Hardware Requirements
The PIC12C67X and PIC12CE67X requires two pro-
grammable power supplies, one for VDD (2.0V to 6.0V
recommended) and one for VPP (12V to 14V). Both
supplies should have a minimum resolution of 0.25V.
1.2 Programming Mode
The programming mode for the PIC12C67X and
PIC12CE67X allows programming of user program
memory, special locations used for ID, and the configu-
ration word for the PIC12C67X and PIC12CE67X.
Pin Diagram:
PDIP
VDD
GP5/OSC1/CLKIN
GP4/OSC2/AN3/
CLKOUT
GP3/MCLR/VPP
1
2
3
4
8 VSS
7 GP0/AN0
6 GP1/AN1/VREF
5 GP2/T0CKI/
AN2/INT
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12C671/672 and PIC12CE673/674
Pin Name
Pin Name
GP1
CLOCK
GP0
DATA
GP3/MCLR/VPP
VPP
VDD
VDD
VSS
VSS
Legend: I = Input, O = Output, P = Power
During Programming
Pin Type
Pin Description
I Clock input
I/O Data input/output
P Programming Power
P Power Supply
P Ground
© 1998 Microchip Technology Inc.
DS40175A-page 1




PIC12C672 pdf, 반도체, 판매, 대치품
PIC12C67X and PIC12CE67X
2.2 Program/Verify Mode
The program/verify mode is entered by holding pins
GP1 and GP0 low while raising MCLR pin from VIL to
VIHH (high voltage). VDD is then raised from VIL to
VIH.Once in this mode the user program memory and
the configuration memory can be accessed and pro-
grammed in serial fashion. The mode of operation is
serial, and the memory that is accessed is the user pro-
gram memory. GP1 is a Schmitt Trigger input in this
mode.
The sequence that enters the device into the program-
ming/verify mode places all other logic into the reset
state (the MCLR pin was initially at VIL). This means
that all I/O are in the reset state (High impedance
inputs).
Note 1: The MCLR pin must be raised from VIL to
VIHH before VDD is applied. This is to
ensure that the device does not have the
PC incremented while in valid operation
range.
Note 2: Do not power GP2, GP4 or GP5 before
VDD is applied.
1.0.1 PROGRAM/VERIFY OPERATION
The GP1 pin is used as a clock input pin, and the GP0
pin is used for entering command bits and data
input/output during serial operation. To input a com-
mand, the clock pin (GP1) is cycled six times. Each
command bit is latched on the falling edge of the clock
with the least significant bit (LSB) of the command
being input first. The data on pin GP0 is required to
have a minimum setup and hold time (see AC/DC
specs) with respect to the falling edge of the clock.
Commands that have data associated with them (read
and load) are specified to have a minimum delay of 1µs
between the command and the data. After this delay
the clock pin is cycled 16 times with the first cycle being
a start bit and the last cycle being a stop bit. Data is
also input and output LSB first. Therefore, during a
read operation the LSB will be transmitted onto pin
GP0 on the rising edge of the second cycle, and during
a load operation the LSB will be latched on the falling
edge of the second cycle. A minimum 1µs delay is also
specified between consecutive commands.
All commands are transmitted LSB first. Data words
are also transmitted LSB first. The data is transmitted
on the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1µs is required between a command and a data word
(or another command).
The commands that are available are listed
in Table 1-1.
1.0.1.1 LOAD CONFIGURATION
After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
to the clock pin, the chip will load 14-bits a “data word”
as described above, to be programmed into the config-
uration memory. A description of the memory mapping
schemes for normal operation and configuration mode
operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user pro-
gram memory is to exit the program/verify test mode by taking MCLR low (VIL).
TABLE 1-1: COMMAND MAPPING
Command
Load Configuration
Load Data
Read Data
Increment Address
Begin programming
End Programming
Mapping (MSB ... LSB)
Data
0 0 0 0 0 0 0, data(14), 0
0 0 0 0 1 0 0, data(14), 0
0 0 0 1 0 0 0, data(14), 0
000110
001000
001110
DS40175A-page 4
© 1998 Microchip Technology Inc.

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PIC12C672 전자부품, 판매, 대치품
EPROM Memory Programming Specification
1.0.1.2 LOAD DATA
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. A timing diagram for the load data
command is shown in Figure 4-1.
1.0.1.3 READ DATA
After receiving this command, the chip will transmit
data bits out of the memory currently accessed starting
with the second rising edge of the clock input. The GP0
pin will go into output mode on the second rising clock
edge, and it will revert back to input mode (hi-imped-
ance) after the 16th rising edge. A timing diagram of
this command is shown in Figure 4-2.
1.0.1.4 INCREMENT ADDRESS
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 4-3.
1.0.1.5 BEGIN PROGRAMMING
A load command (load configuration or load data)
must be given before every begin programming
command. Programming of the appropriate memory
(test program memory or user program memory) will
begin after this command is received and decoded.
Programming should be performed with a series of
100µs programming pulses. A programming pulse is
defined as the time between the begin programming
command and the end programming command.
1.0.1.6 END PROGRAMMING
After receiving this command, the chip stops program-
ming the memory (configuration program memory or
user program memory) that it was programming at the
time.
1.1 Programming Algorithm Requires
Variable VDD
The PIC12C67X and PIC12CE67X uses an intelligent
algorithm. The algorithm calls for program verification
at VDDmin as well as VDDmax. Verification at VDDmin
guarantees good “erase margin”. Verification at
VDDmax guarantees good “program margin”.
The actual programming must be done with VDD in the
VDDP range (4.75 - 5.25V).
VDDP = VCC range required during programming.
VDD min. = minimum operating VDD spec for the part.
VDD max.= maximum operating VDD spec for the part.
Programmers must verify the PIC12C67X and
PIC12CE67X at its specified VDDmax and VDDmin lev-
els. Since Microchip may introduce future versions of
the PIC12C67X and PIC12CE67X with a broader VDD
range, it is best that these levels are user selectable
(defaults are ok).
Note:
Any programmer not meeting these
requirements may only be classified as
“prototype” or “development” programmer
but not a “production” quality programmer.
© 1998 Microchip Technology Inc.
DS40175A-page 7

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