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부품번호 | M40Z111WMH 기능 |
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기능 | NVRAM CONTROLLER for up to TWO LPSRAM | ||
제조업체 | ST Microelectronics | ||
로고 | |||
전체 12 페이지수
M40Z111
M40Z111W
NVRAM CONTROLLER for up to TWO LPSRAM
CONVERT LOW POWER SRAMs into
NVRAMs
PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
AUTOMATIC WRITE-PROTECTION when VCC
is OUT-OF-TOLERANCE
CHOICE of SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
– M40Z111:
VCC = 4.5V to 5.5V
THS = VSS 4.5V ≤ VPFD ≤ 4.75V
THS = VOUT 4.2V ≤ VPFD ≤ 4.5V
– M40Z111W:
VCC = 3.0V to 3.6V
THS = VSS 2.8V ≤ VPFD ≤ 3.0V
VCC = 2.7V to 3.3V
THS = VOUT 2.5 ≤ VPFD ≤ 2.7V
LESS THAN 15ns CHIP ENABLE ACCESS
PROPAGATION DELAY (for 5.0V device)
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
Figure 1. Logic Diagram
VCC
DESCRIPTION
The M40Z111/111W NVRAM Controller is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory.
A precision voltage reference and comparator
monitors the VCC input for an out-of-tolerance con-
dition.
Table 1. Signal Names
THS
Threshold Select Input
E Chip Enable Input
ECON
VOUT
VCC
VSS
Conditioned Chip Enable Output
Supply Voltage Output
Supply Voltage
Ground
THS
E
M40Z111
M40Z111W
VSS
VOUT
ECON
AI02238B
February 1999
1/12
M40Z111, M40Z111W
Table 3. AC Measurement Condition
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages 1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Manufacturers generally specify a typical condition
for room temperature along with a worst case
condition (generally at elevated temperatures). The
system level requirements will determine the
choice of which value to use. The data retention
current value of the SRAMs can then be added to
the ICCDR value of the M40Z111/111W to determine
the total current requirements for data retention.
The available battery capacity for the SNAPHAT of
your choice can then be divided by this current to
determine the amount of data retention available
(see Table 7). For more information on Battery
Storage Life refer to the Application Note AN1012.
VCC NOISE AND NEGATIVE-GOING TRAN-
SIENTS
ICC transients, including those produced by output
switching, can produce voltage fluctuations, result-
ing in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur.
Figure 4. AC Testing Load Circuit
DEVICE
UNDER
TEST
645Ω
CL = 100pF
or 5pF
1.75V
CL includes JIG capacitance
AI02326
A ceramic bypass capacitor value of 0.1µF (as
shown in Figure 4) is recommended in order to
provide the needed filtering. In addition to tran-
sients that are caused by normal SRAM operation,
power cycling can generate negative voltage
spikes on VCC that drive it to values below VSS by
as much as one volt. These negative spikes can
cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage
spikes, ST recommends connecting a schottky di-
ode from VCC to VSS (cathode connected to VCC,
anode to VSS).
Table 4. Capacitance (1)
(TA = 25°C; f = 1MHz)
Symbol
Parameter
CIN Input Capacitance
COUT (2)
Output Capacitance
Note: 1. Sampled only, not 100% tested.
2. Outputs deselected.
Test Condition Min Max Unit
VIN = 0V
8 pF
VOUT = 0V
10 pF
4/12
4페이지 M40Z111, M40Z111W
Table 6. Power Down/Up AC Characteristics
(TA = 0 to 70°C)
Symbol
tF (1)
tFB (2)
tR
Parameter
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSO VCC Fall Time
VPFD(min) to VPFD (max) VCC Rise Time
Min Max Unit
300 µs
10 µs
10 µs
tEDL Chip Enable Propagation Delay
M40Z111
M40Z111W
15 ns
20 ns
tEDH Chip Enable Propagation Delay
M40Z111
M40Z111W
10 ns
20 ns
tER Chip Enable Recovery
40 200 ms
tWP Write Protect Time
M40Z111
M40Z111W
40 150 µs
40 250 µs
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down Timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO
tF
E
ECON
tFB
tWPT
VOHB
AI02396
7/12
7페이지 | |||
구 성 | 총 12 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
M40Z111WMH | NVRAM CONTROLLER for up to TWO LPSRAM | ST Microelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |