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M41T315V-65MH6TR 데이터시트 PDF




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부품번호 M41T315V-65MH6TR 기능
기능 Serial Access Phantom RTC Supervisor
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M41T315V-65MH6TR 데이터시트, 핀배열, 회로
M41T315Y*
M41T315V/W
Serial Access Phantom RTC Supervisor
FEATURES SUMMARY
3.0V, 3.3V, OR 5V OPERATING VOLTAGE
REAL TIME CLOCK KEEPS TRACK OF
TENTHS/HUNDREDTHS OF SECONDS,
SECONDS, MINUTES, HOURS, DAYS,
DATE OF THE MONTH, MONTHS, AND
YEARS
AUTOMATIC LEAP YEAR CORRECTION
VALID UP TO 2100
AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY
CHOICE OF POWER-FAIL DESELECT
VOLTAGES:
(VPFD = Power-fail Deselect Voltage)
– M41T315Y: VCC = 4.5 to 5.5V
4.25V VPFD 4.50V
– M41T315V: VCC = 3.0 to 3.6V
2.80V VPFD 2.97V
– M41T315W: VCC = 2.7 to 3.3V
2.60V VPFD 2.70V
NO ADDRESS SPACE REQUIRED TO
COMMUNICATE WITH RTC
PROVIDES NONVOLATILE SUPERVISOR
FUNCTIONS FOR BATTERY BACKUP OF
SRAM
FULL ±10% VCC OPERATING RANGE
INDUSTRIAL OPERATING TEMPERATURE
RANGE (–40 to +85°C)
ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (max)
OPTIONAL PACKAGING INCLUDES A 28-
LEAD SOIC and SNAPHAT® TOP (to be
ordered separately)
SNAPHAT PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP,
WHICH CONTAINS THE BATTERY AND
CRYSTAL
Figure 1. 16-pin SOIC Package
16
1
SO16 (MQ)
Figure 2. 28-pin SOIC Package
SNAPHAT (SH)
Battery/Crystal
28
1
SOH28 (MH)
* Contact Local Sales Office
June 2004
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M41T315V-65MH6TR pdf, 반도체, 판매, 대치품
M41T315Y*, M41T315V, M41T315W
SUMMARY DESCRIPTION
The M41T315Y/V/W RTC Supervisor is a combi-
nation of a CMOS TIMEKEEPER® and a nonvola-
tile memory supervisor. Power is constantly
monitored by the memory supervisor. In the event
of power instability or absence, an external battery
maintains the timekeeping operation and provides
power for a CMOS static RAM by switching on and
invoking write protection to prevent data corrup-
tion in the memory and RTC.
The clock keeps track of tenths/hundredths of sec-
onds, seconds, minutes, hours, day, date, month,
and year information. The last day of the month is
automatically adjusted for months with less than
31 days, including leap year correction.
The clock operates in one of two formats:
– a 12-hour mode with an AM/PM indicator;
or
– a 24-hour mode
The nonvolatile supervisor supplies all the neces-
sary support circuitry to convert a CMOS RAM to
a nonvolatile memory. The M41T315Y/V/W can
be interfaced with RAM without leaving gaps in
memory.
The M41T315Y/V/W is supplied in a 28-lead SOIC
SNAPHAT® package (which integrates both crys-
tal and battery in a single SNAPHAT top) or a-16
pin SOIC. The 28-pin, 330mil SOIC provides sock-
ets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The 28-pin SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4TXX-BR12SH” (see Table
17., page 22).
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
Figure 3. Logic Diagram
VCCI VCCO
D
(1)
XI
(1)
XO
WE
CEI
OE
RST
M41T315Y
M41T315V
M41T315W
(1)
VBAT VSS
Q
CEO
AI03902
4/24
Note: 1. For 16-pin SOIC only
Table 1. Signal Names
XI-XO
32.768 kHz Crystal Connection
D Data Input
Q Data Output
RST
Reset Input
CEO
Chip Enable Output
CEI Chip Enable Input
VBAT
Battery Input
OE Output Enable Input
WE WRITE Enable Input
VCCO
Switched Supply Voltage Output
VCCI
Supply Voltage Input
VSS
Ground
NC Not Connected Internally
DU Don’t Use

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M41T315V-65MH6TR 전자부품, 판매, 대치품
M41T315Y*, M41T315V, M41T315W
OPERATION
Figure 6., page 5 illustrates the main elements of
the device. The following paragraphs describe the
signals and functions.
Communication with the clock is established by
pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecu-
tive WRITE cycles containing the proper data on
data in (D). All accesses which occur prior to rec-
ognition of the 64-bit pattern are directed to mem-
ory via the chip enable output pin (CEO).
After recognition is established, the next 64 READ
or WRITE Cycles either extract or update data in
the clock and CEO remains high during this time,
disabling the connected memory (see Table
2., page 7).
Data transfer to and from the timekeeping function
is accomplished with a serial bit stream under con-
trol of chip enable input (CEI), output enable (OE),
and WRITE enable (WE). Initially, a READ cycle
using the CEI and OE control of the clock starts the
pattern recognition sequence by moving the point-
er to the first bit of the 64-bit comparison register.
Next, 64 consecutive WRITE cycles are executed
using the CEI and WE control of the clock. These
64 WRITE cycles are used only to gain access to
the clock.
When the first WRITE cycle is executed, it is com-
pared to the first bit of the 64-bit comparison reg-
ister. If a match is found, the pointer increments to
the next location of the comparison register and
awaits the next WRITE cycle.
If a match is not found, the pointer does not ad-
vance and all subsequent WRITE cycles are ig-
nored. If a READ cycle occurs at any time during
pattern recognition, the present sequence is abort-
ed and the comparison register pointer is reset.
Pattern recognition continues for a total of 64
WRITE cycles as described above until all the bits
in the comparison register have been matched
(see Figure 10., page 11.)
With a correct match for 64 bits, access to the reg-
isters is enabled and data transfer to or from the
timekeeping registers may proceed. The next 64
cycles will cause the device to either receive data
on D, or transmit data on Q, depending on the lev-
el of OE pin or the WE pin. Cycles to other locations
outside the memory block can be interleaved with
CEI cycles without interrupting the pattern recogni-
tion sequence or data transfer sequence to the de-
vice.
For a SO16 pin package, a standard 32.768 kHz
quartz crystal can be directly connected to the
M41T315Y/V/W via pins 1 and 2 (XI, XO). The
crystal selected for use should have a specified
load capacitance (CL) of 12.5 pF (see Table
10., page 17).
Table 2. Operating Modes
Mode
VCC CEI OE
Deselect
WRITE
READ
READ
4.5 to 5.5V
or
3.0 to 3.6V
or
2.7 to 3.3V
VIH X
VIL X
VIL VIL
VIL VIH
Deselect
VSO to VPFD (min)(1)
X
X
Deselect
VSO(1)
XX
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Note: 1. See Table 11., page 17 for details.
WE
X
VIL
VIH
VIH
X
X
D
Hi-Z
DIN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Q
Hi-Z
Hi-Z
DOUT
Hi-Z
Hi-Z
Hi-Z
Power
Standby
Active
Active
Active
CMOS Standby
Battery Back-up Mode
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부품번호상세설명 및 기능제조사
M41T315V-65MH6TR

Serial Access Phantom RTC Supervisor

ST Microelectronics
ST Microelectronics

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