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PDF M48Z12 Data sheet ( Hoja de datos )
| Número de pieza | M48Z12 | |
| Descripción | 16 Kbit (2 Kb x 8) ZEROPOWER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48Z02
M48Z12
5 V, 16 Kbit (2 Kb x 8) ZEROPOWER® SRAM
Features
■ Integrated, ultra low power SRAM and power-
fail control circuit
■ Unlimited WRITE cycles
■ READ cycle time equals WRITE cycle time
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages
(VPFD = power-fail deselect voltage):
– M48Z02: VCC= 4.75 to 5.5 V;
4.5 V ≤ VPFD ≤ 4.75 V
– M48Z12: VCC= 4.5 to 5.5 V;
4.2 V ≤ VPFD ≤ 4.5 V
■ Self-contained battery in the CAPHAT™ DIP
package
■ Pin and function compatible with JEDEC
standard 2 K x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
24
1
PCDIP24
Battery CAPHAT™
June 2011
Doc ID 2420 Rev 9
1/22
www.st.com
1
1 page  
M48Z02, M48Z12
1 Description
Description
The M48Z02/12 ZEROPOWER® RAM is a 2 K x 8 non-volatile static RAM which is pin and
function compatible with the DS1220.
A special 24-pin, 600 mil DIP CAPHAT™ package houses the M48Z02/12 silicon with a
long-life lithium button cell to form a highly integrated battery-backed memory solution.
The M48Z02/12 button cell has sufficient capacity and storage life to maintain data
functionality for an accumulated time period of at least 10 years in the absence of power
over commercial operating temperature range.
The M48Z02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2 K x 8
SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed.
Figure 1. Logic diagram
VCC
11
A0-A10
8
DQ0-DQ7
W M48Z02
M48Z12
E
G
VSS
Table 1. Signal names
A0-A10
Address inputs
DQ0-DQ7
Data inputs / outputs
E Chip enable
G Output enable
W WRITE enable
VCC Supply voltage
VSS Ground
AI01186
Doc ID 2420 Rev 9
5/22
5 Page 
M48Z02, M48Z12
Figure 7. Checking the BOK flag status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
Operation modes
IS DATA
COMPLEMENT
OF FIRST
READ?
(BATTERY OK) YES
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
NO (BATTERY LOW)
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
CONTINUE
AI00607
Doc ID 2420 Rev 9
11/22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet M48Z12.PDF ] | |
Hoja de datos destacado
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