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부품번호 | M48Z129V 기능 |
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기능 | 1 Mbit (128 Kb x 8) ZEROPOWER SRAM | ||
제조업체 | ST Microelectronics | ||
로고 | |||
전체 20 페이지수
M48Z129V
3.3 V, 1 Mbit (128 Kb x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ Conventional SRAM operation; unlimited
)WRITE cycles
t(s■ 10 years of data retention in the absence of
cpower
du■ Microprocessor power-on reset (reset valid
roeven during battery backup mode)
P■ Battery low pin - provides warning of battery
end-of-life
lete■ Automatic power-fail chip deselect and WRITE
protection
so■ WRITE protect voltages
Ob– VCC = 3.0 to 3.6 V; 2.7 V ≤ VPFD ≤ 3.0 V
-(VPFD = power-fail deselect voltage)
)■ Self-contained battery in the CAPHAT™ DIP
t(spackage
c■ Pin and function compatible with JEDEC
ustandard 128 K x 8 SRAMs
rod■ RoHS compliant
Obsolete P– Lead-free second level interconnect
32
1
PMDIP32 module
September 2011
Doc ID 5716 Rev 8
This is information on a product still in production but not recommended for new designs.
1/20
www.st.com
1
List of figures
List of figures
M48Z129V
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Figure 6. WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9.
Figure 10.
)Figure 11.
Obsolete Product(s) - Obsolete Product(sFigure 12.
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic module DIP, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4/20 Doc ID 5716 Rev 8
4페이지 M48Z129V
2 Operation modes
Operation modes
The M48Z129V also has its own power-fail detect circuit. This control circuitry constantly
monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance,
the circuit write protects the SRAM, providing data security in the midst of unpredictable
system operation. As VCC falls, the control circuitry automatically switches to the battery,
maintaining data until valid power is restored.
Table 2. Operating modes
Mode
VCC
E G W DQ0-DQ7
Power
te Product(s)Note:
Obsolete Product(s) - Obsole2.1
Deselect
WRITE
READ
4.5 to 5.5 V
or
3.0 to 3.6 V
VIH X
X
VIL X VIL
VIL VIL VIH
READ
VIL VIH VIH
Deselect VSO to VPFD (min)(1)
X
X
X
Deselect
≤ VSO(1)
XXX
1. See Table 10 for details.
X = VIH or VIL; VSO = battery backup switchover voltage
High Z
DIN
DOUT
High Z
High Z
High Z
Standby
Active
Active
Active
CMOS standby
Battery backup mode
READ mode
The M48Z129V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 17 address inputs defines which one of
the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within tAVQV (address access time) after the last address input signal is stable, providing the
E and G access times are also satisfied. If the E and G access times are not met, valid data
will be available after the latter of the chip enable access times (tELQV) or output enable
access time (tGLQV).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the address inputs are changed while E and G remain active, output data will remain valid
for tAXQX (output data hold time) but will go indeterminate until the next address access.
Figure 4. Address controlled, READ mode AC waveforms
Note:
A0-A16
DQ0-DQ7
tAXQX
tAVQV
tAVAV
VALID
DATA VALID
DATA VALID
Chip enable (E) and output enable (G) = low, WRITE enable (W) = high
AI02324
Doc ID 5716 Rev 8
7/20
7페이지 | |||
구 성 | 총 20 페이지수 | ||
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
M48Z129V | 1 Mbit (128 Kb x 8) ZEROPOWER SRAM | ST Microelectronics |
M48Z129Y | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM | ST Microelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |