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M48Z2M1 데이터시트 PDF




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부품번호 M48Z2M1 기능
기능 16 Mb 2Mb x 8 ZEROPOWER SRAM
제조업체 ST Microelectronics
로고 ST Microelectronics 로고


M48Z2M1 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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M48Z2M1 데이터시트, 핀배열, 회로
M48Z2M1
M48Z2M1Y
16 Mb (2Mb x 8) ZEROPOWER® SRAM
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERIES
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z2M1: 4.5V VPFD 4.75V
– M48Z2M1Y: 4.2V VPFD 4.50V
BATTERIES ARE INTERNALLY ISOLATED
UNTIL POWER IS APPLIED
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2Mb x 8 SRAMs
36
1
PMLDIP36 (PL)
Module
Figure 1. Logic Diagram
DESCRIPTION
The M48Z2M1/2M1Y ZEROPOWER® RAM is a
non-volatile 16,777,216 bit Static RAM organized
as 2,097,152 words by 8 bits. The device combines
two internal lithium batteries, CMOS SRAMs and a
control circuit in a plastic 36 pin DIP long Module.
The ZEROPOWER RAM replaces industry stand-
ard SRAMs. It provides the nonvolatility of PROMs
without any requirement for special write timing or
limitations on the number of writes that can be
performed.
Table 1. Signal Names
A0-A20
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E Chip Enable
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
VCC
21
A0-A20
8
DQ0-DQ7
W M48Z2M1
M48Z2M1Y
E
G
VSS
AI02048
January 1998
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/12




M48Z2M1 pdf, 반도체, 판매, 대치품
M48Z2M1, M48Z2M1Y
Table 5. Capacitance (1, 2)
(TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition Min Max Unit
CIN Input Capacitance
VIN = 0V
CIO (3)
Input / Output Capacitance
VOUT = 0V
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected
40 pF
40 pF
Table 6. DC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
ILI (1)
ILO (1)
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0V VIN VCC
0V VOUT VCC
ICC Supply Current
E = VIL, Outputs open
ICC1 Supply Current (Standby) TTL
ICC2 Supply Current (Standby) CMOS
E = VIH
E VCC – 0.2V
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
IOL = 2.1mA
VOH Output High Voltage
Note: 1. Outputs deselected.
IOH = –1mA
Min
–0.3
2.2
2.4
Max
±4
±4
140
10
8
0.8
VCC + 0.3
0.4
Unit
µA
µA
mA
mA
mA
V
V
V
V
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70°C)
Symbol
Parameter
Min Typ Max Unit
VPFD Power-fail Deselect Voltage (M48Z2M1)
4.5 4.6 4.75 V
VPFD
Power-fail Deselect Voltage (M48Z2M1Y)
4.2 4.3 4.5
V
VSO Battery Back-up Switchover Voltage
tDR(2)
Data Retention Time
Notes: 1. All voltages referenced to VSS.
2. At 25°C
3
10
V
YEARS
4/12

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M48Z2M1 전자부품, 판매, 대치품
M48Z2M1, M48Z2M1Y
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
A0-A20
E
G
DQ0-DQ7
tAVAV
VALID
tAVQV
tELQV
tELQX
tGLQV
tGLQX
tAXQX
tEHQZ
tGHQZ
DATA OUT
AI02052
Note: Write Enable (W) = High.
DATA RETENTION MODE
With valid VCC applied, the M48Z2M1/2M1Y oper-
ates as a conventional BYTEWIDEstatic RAM.
Should the supply voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself tWP after VCC falls below VPFD. All outputs
become high impedance, and all inputs are treated
as "don’t care."
If power fail detection occurs during a valid access,
the memory cycle continues to completion. If the
memory cycle fails to terminate within the time tWP,
write protection takes place. When VCC drops be-
low VSO, the control circuit switches power to the
internal energy source which preserves data.
The internal coin cells will maintain data in the
M48Z2M1/2M1Y after the initial application of VCC
for an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns and
VCC rises above VSO, the batteries are discon-
nected, and the power supply is switched to exter-
nal Vcc. Write protection continues for tER after VCC
reaches VPFD to allow for processor stabilization.
After tER, normal RAM operation can resume.
For more information on Battery Storage life refer
to the Application Note AN1012.
7/12

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