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PDF M48Z35AV Data sheet ( Hoja de datos )
| Número de pieza | M48Z35AV | |
| Descripción | 256 Kbit (32 Kbit x 8) ZEROPOWER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48Z35AV
5.0 V or 3.3 V, 256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ READ cycle time equals WRITE cycle time
)■ Battery low flag (BOK)
t(s■ Automatic power-fail chip deselect and WRITE
cprotection
du■ WRITE protect voltage:
ro(VPFD = power-fail deselect voltage)
P– M48Z35AV: 2.7 V ≤ VPFD ≤ 3.0 V
te■ Self-contained battery in the CAPHAT™ DIP
lepackage
o■ Packaging includes a 28-lead SOIC and
sSNAPHAT® top (to be ordered separately)
Ob■ Pin and function compatible with JEDEC
-standard 32 Kbit x 8 SRAMs
t(s)■ SOIC package provides direct connection for a
SNAPHAT® top which contains the battery
c■ RoHS compliant
Obsolete Produ– Lead-free second level interconnect
28
1
PCDIP28
Battery CAPHAT™
SNAPHAT®
battery
28
1
SOH28
June 2011
Doc ID 6784 Rev 9
This is information on a product still in production but not recommended for new designs.
1/25
www.st.com
1
1 page  
M48Z35AV
1 Description
Description
The M48Z35AV ZEROPOWER® RAM is a 32 Kbit x 8, non-volatile static RAM that
integrates power-fail deselect circuitry and battery control logic on a single die. The
monolithic chip is available in two special packages to provide a highly integrated battery-
backed memory solution.
The M48Z35AV is a non-volatile pin and function equivalent to any JEDEC standard 32 K x8
SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed. The 28-pin 600 mil DIP CAPHAT™ houses
the M48Z35AV silicon with a long life lithium button cell in a single package.
)The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
t(sconnection to a separate SNAPHAT® housing containing the battery. The unique design
allows the SNAPHAT battery package to be mounted on top of the SOIC package after the
ccompletion of the surface mount process. Insertion of the SNAPHAT housing after reflow
duprevents potential battery damage due to the high temperatures required for device surface-
romounting. The SNAPHAT housing is keyed to prevent reverse insertion.
PThe SOIC and battery packages are shipped separately in plastic anti-static tubes or in tape
te& reel form.
leFor the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is “M4Z28-
oBR00SH1.”
- ObsFigure 1. Logic diagram
VCC
ct(s) 15
du A0-A14
8
DQ0-DQ7
Pro W
M48Z35AV
lete E
Obso G
VSS
AI02781B
Doc ID 6784 Rev 9
5/25
5 Page 
M48Z35AV
Operating modes
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48Z35AV
–100
Unit
Min Max
tAVAV
WRITE cycle time
100 ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0 ns
tWLWH
WRITE enable pulse width
80 ns
tELEH
Chip enable low to chip enable high
80
ns
uct(s) - Obsolete Product(s)2.3
Obsolete ProdNote:
tWHAX
tEHAX
tDVWH
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
10
10
50
tDVEH
Input valid to chip enable high
50
tWHDX
tEHDX
tWLQZ(2)(3)
tAVWH
tAVEH
tWHQX(2)(3)
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
5
5
50
80
80
10
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
2. CL = 5 pF (see Figure 10 on page 15).
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data retention mode
With valid VCC applied, the M48Z35AV operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48Z35AV may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data. The internal button cell will maintain data in the M48Z35AV for an
accumulated period of at least 10 years (at 25°C) when VCC is less than VSO.
As system power returns and VCC rises above VSO, the battery is disconnected, and the
power supply is switched to external VCC. Write protection continues until VCC reaches
VPFD(min) plus tREC(min). Normal RAM operation can resume tREC after VCC exceeds
VPFD(max).
Doc ID 6784 Rev 9
11/25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet M48Z35AV.PDF ] | |
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