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PDF MG64P Data sheet ( Hoja de datos )
| Número de pieza | MG64P | |
| Descripción | 0.25m Embedded DRAM/ Customer Structured Arrays | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MG64P (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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DATA SHEET
OKI
ASIC
PRODUCTS
MG63P/64P/65P
0.25µm Embedded DRAM/
Customer Structured Arrays
November 1998
1 page  
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG63P/64P/65P s
I/O base cells
Configurable I/O pads
for VDD, VSS, or I/O
Separate power bus (VDDC, VSSC) for
internal core logic (2nd metal/3rd metal)
1, 2, 3, 4, or 5 layer
metal
interconnection in
core area
Core base cell
with 4 transistors
VDD, VSS pads (4) in each
corner for wafer probing only
Separate power bus (VDDO, VSSO) over I/O cell
for output buffers (2nd metal/3rd metal)
Figure 7. MG65P Array Architecture
MG63P/64P/65P CSA Layout Methodology
The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
- Identify megacell functions (e.g. embedded SDRAM) required and minimum array size to
hold macrocell functions.
- Add together all the area occupied by the required random logic and macrocells and select
the optimum array.
2. Make a floor plan for the design’s megacells.
- Oki Design Center engineers verify the master slice and review simulation.
- Oki Design Center or customer engineers floorplan the array using Oki’s supported Cadence
DP3 or Gambit GFP and customer performance specifications.
- Using Oki CAD software, Design Center engineers remove the SOG transistors and replace
them with diffused memory macrocells to the customer’s specifications.
Oki Semiconductor
3
5 Page 
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG63P/64P/65P s
AC Characteristics (Core VDD = 2.5 V, VSS = 0 V, Tj = 25°C)
Parameter
Driving Type
Conditions [1] [2]
Internal gate
propagation delay
Inverter
1X
2X
4X
2-input NAND
1X F/O = 2, L = 0 mm
2X VDD = 2.5 V
4X
2-input NOR
1X
4X
Inverter
1X
2X
2-input NAND
4X
1X F/O = 2, L = standard
wire length
2X VDD = 2.5 V
4X
2-input NOR
1X
4X
Toggle frequency
F/O = 1, L = 0 mm
Rated Value [3]
0.091
0.079
0.065
0.13
0.11
0.09
0.16
0.13
0.24
0.18
0.12
0.30
0.20
0.14
0.41
0.24
1100
1. Input transition time in 0.15 ns / 2.5 V.
2. Typical condition in VDD = 2.5 V and Tj = 25oC for a typical process.
3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process.
AC Characteristics (I/O VDD = 3.3 V, VSS = 0 V, Tj = 25°C)
Parameter
Conditions
Input buffer propagation delay
F/O = 2, L = standard wire length
Output buffer
propagation delay
Push-pull
Normal Output
4 mA
8 mA
CL = 20 pF
CL = 50 pF
Buffer
12mA CL = 100 pF
Output buffer
transition time [1]
Push-pull
Normal output
12 mA CL = 100 pF
Buffer
1. Output rising and falling times are both specified over a 10 to 90% range.
Rated Value
0.29
1.73
1.96
2.52
3.79 (r)
3.07 (f)
Unit
ns
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
Oki Semiconductor
9
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MG64P.PDF ] | |
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