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부품번호 | 74LVQ02 기능 |
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기능 | QUAD 2-INPUT NOR GATE | ||
제조업체 | STMicroelectronics | ||
로고 | |||
전체 8 페이지수
® 74LVQ02
QUAD 2-INPUT NOR GATE
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.3 V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 02
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ02 is a low voltage CMOS QUAD
2-INPUT NOR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ02M
74LVQ02T
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/8
74LVQ02
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symb ol
Parameter
T est Con ditio n
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
tPLH Propagation Delay Time
tPHL
2.7
3.3(*)
6.0 10.5
5.0 7.5
12.0 ns
8.0
tOSLH Output to Output Skew
tOSHL Time (note 1, 2)
2.7
3.3(*)
0.5 1.5
0.5 1.5
1.5 ns
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
CIN Input Capacitance
3.3
4 pF
CPD Power Dissipation
3.3 fIN = 10 MHz
Capacitance (note 1)
40
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC •fIN + ICC/4(per gate)
4/8
4페이지 DIM.
A
A1
A2
b
c
D
E
E1
e
K
L
74LVQ02
TSSOP14 MECHANICAL DATA
MIN.
0.05
0.85
0.19
0.09
4.9
6.25
4.3
0o
0.50
mm
TYP.
0.10
0.9
5
6.4
4.4
0.65 BSC
4o
0.60
MAX.
1.1
0.15
0.95
0.30
0.20
5.1
6.5
4.48
8o
0.70
MIN.
0.002
0.335
0.0075
0.0035
0.193
0.246
0.169
0o
0.020
inch
TYP.
0.004
0.354
0.197
0.252
0.173
0.0256 BSC
4o
0.024
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.201
0.256
0.176
8o
0.028
A A2
A1 b
e
D
c
KL
E
PIN 1 IDENTIFICATION
1
E1
7/8
7페이지 | |||
구 성 | 총 8 페이지수 | ||
다운로드 | [ 74LVQ02.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
74LVQ00 | QUAD 2-INPUT NAND GATE | STMicroelectronics |
74LVQ00 | Low Voltage Quad 2-Input NAND Gate | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |