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PDF 74LVQ138 Data sheet ( Hoja de datos )
| Número de pieza | 74LVQ138 | |
| Descripción | Low Voltage 1-of-8 Decoder/Demultiplexer | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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May 1998
74LVQ138
Low Voltage 1-of-8 Decoder/Demultiplexer
General Description
The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables al-
low parallel expansion to a 1-of-24 decoder using just three
LVQ138 devices or a 1-of-32 decoder using four LVQ138 de-
vices and one inverter.
Features
n Ideal for low power/low noise 3.3V applications
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75Ω
n 4 kV minimum ESD immunity
n Demultiplexing capability
n Multiple input enable for each expansion
n Active LOW mutually exclusive outputs
Ordering Code:
Order Number Package Number
Package Description
74LVQ138SC
M16A
16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC
74LVQ138SJ
M16D
16-Lead Molded Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for SOIC JEDEC and EIAJ
DS011350-1
IEEE/IEC
DS011350-4
DS011350-2
Pin Descriptions
Pin Names
A0– A2
E1– E2
E3
O0– O7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
© 1998 Fairchild Semiconductor Corporation DS011350
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
VCC
(V)
TA = +25˚C
CL = 50 pF
TA = −40˚C to +85˚C
CL = 50 pF
Units
Min Typ Max Min Max
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tOSHL,
tOSLH
Propagation Delay
An to On
Propagation Delay
An to On
Propagation Delay
E1 or E2 to On
Propagation Delay
E1 or E2 to On
Propagation Delay
E3 to On
Propagation Delay
E3 to On
Output to Output Skew (Note 9)
Data to Output
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
1.5 10.2 18.3 1.5 21.0 ns
1.5 8.5 13.0 1.5 15.0
1.5 9.6 17.6 1.5 20.0 ns
1.5 8.0 12.5 1.5 14.0
1.5 13.2 21.0 1.5 23.0 ns
1.5 11.0 15.0 1.5 16.0
1.5 11.4 19.0 1.5 21.0 ns
1.5 9.5 13.5 1.5 15.0
1.5 13.2 21.8 1.5 23.5 ns
1.5 11.0 15.5 1.5 16.5
1.5 10.2 18.3 1.5 20.0 ns
1.5 8.5 13.0 1.5 14.0
1.0 1.5
1.5 ns
1.0 1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
CIN
CPD (Note 10)
Note 10: CPD is measured at 10 MHz.
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ Units
Conditions
4.5 pF VCC = Open
45 pF VCC = 3.3V
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74LVQ138.PDF ] | |
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