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부품번호 | 74LVQ174 기능 |
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기능 | Low Voltage Hex D-Type Flip-Flop with Master Reset | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 6 페이지수
May 1998
74LVQ174
Low Voltage Hex D-Type Flip-Flop with Master Reset
General Description
The LVQ174 is a high-speed hex D-type flip-flop. The device
is used primarily as a 6-bit edge-triggered storage register.
The information on the D inputs is transferred to storage dur-
ing the LOW-to-HIGH clock transition. The device has a
Master Reset to simultaneously clear all flip-flops.
Features
n Ideal for low power/low noise 3.3V applications
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Guaranteed pin-to-pin skew AC performance
n Guaranteed incident wave switching into 75Ω
Ordering Code:
Order Number
74LVQ174SC
74LVQ174SJ
Package Number
M16A
M16D
Package Description
16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC
16-Lead Molded Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC JEDEC and EIAJ
IEEE/IEC
DS011353-1
DS011353-2
DS011353-3
Pin Descriptions
Pin Names
D0– D5
CP
MR
Q0– Q5
Description
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
© 1998 Fairchild Semiconductor Corporation DS011353
www.fairchildsemi.com
AC Electrical Characteristics
Symbol
Parameter
VCC
(V)
TA = +25˚C
CL = 50 pF
TA = −40˚C to +85˚C
CL = 50 pF
Units
Min Typ Max Min Max
fmax Maximum Clock
Frequency
2.7
3.3 ±0.3
60
90
90
100
50 MHz
70
tPLH Propagation Delay
2.7 2.0 10.8 16.2 1.5 18.0 ns
CP to Qn
3.3 ±0.3
2.0
9.0 11.5 1.5 12.5
tPHL Propagation Delay
2.7 2.0 10.2 15.5 1.5 17.0 ns
CP to Qn
3.3 ±0.3
2.0
8.5 11.0 1.5 12.0
tPHL Propagation Delay
2.7 2.5 10.8 16.2 2.0 18.0 ns
MR to Qn
3.3 ±0.3
2.5
9.0 11.5 2.0 12.5
tOSHL,
Output to
2.7
1.0 1.5
1.5 ns
tOSLH
Output Skew (Note 9)
3.3 ±0.3
1.0 1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW MR Pulse Width, LOW
tW CP Pulse Width
trec Recovery Time
MR to CP
VCC
(V)
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
Capacitance
Symbol
CIN
CPD (Note 10)
Parameter
Input Capacitance
Power Dissipation
Capacitance
Note 10: CPD is measured at 10 MHz.
TA = +25˚C
CL = 50 pF
Typ
TA = −40˚C to +85˚C
CL = 50 pF
Guaranteed Minimum
3.0 8.0
10.0
2.5 6.5
7.0
1.2 4.0
4.5
1.0 3.0
3.0
1.2 7.0
10.0
1.0 5.5
7.0
1.2 7.0
10.0
1.0 5.5
7.0
0 3.5
3.5
0 2.5
2.5
Units
ns
ns
ns
ns
ns
Typ Units
Conditions
4.5 pF VCC = Open
23 pF VCC = 3.3V
www.fairchildsemi.com
4
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부품번호 | 상세설명 및 기능 | 제조사 |
74LVQ174 | HEX D-TYPE FLIP FLOP WITH CLEAR | STMicroelectronics |
74LVQ174 | Low Voltage Hex D-Type Flip-Flop with Master Reset | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |