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74LVQ273M PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 74LVQ273M
기능 OCTAL D-TYPE FLIP FLOP WITH CLEAR
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74LVQ273M 데이터시트, 핀배열, 회로
® 74LVQ273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX = 150 MHz (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUT
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.4 V (TYP.) at VCC = 3.3V
s 75TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ273 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology. It is ideal for low
power and low noise 3.3V applications.
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ273M
74LVQ273T
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR inputs is held low, the Q
outputs are held low independentely of the other
inputs .
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
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74LVQ273M pdf, 반도체, 판매, 대치품
74LVQ273
DC SPECIFICATIONS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
VIH High Level Input Voltage 3.0 to
VIL Low Level Input Voltage
3.6
2.0 2.0
0.8 0.8
VOH High Level Output
Voltage
VOL Low Level Output
Voltage
3.0 VI(* ) = IO=-50 µA 2.9 2.99
2.9
VIH or
VIL
IO=-12 mA
IO=-24 mA
2.58
2.48
2.2
3.0 VI(*) = IO=50 µA
0.002 0.1
0.1
VIH or
VIL
IO=12 mA
IO=24 mA
0 0.36
0.44
0.55
II Input Leakage Current
3.6 VI = VCC or GND
±0.1 ±1
ICC Quiescent Supply
Current
3.6 VI = VCC or GND
4 40
IOLD Dynamic Output Current
3.6
VOLD = 0.8 V max
IOHD (note 1, 2)
VOHD = 2 V min
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 .
(*) All outputs loaded.
36
-25
Unit
V
V
V
V
µA
µA
mA
mA
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
VOLP
VOLV
VIHD
Dynamic Low Voltage
Quiet Output (note 1, 2)
Dynamic High Voltage
Input (note 1, 3)
3.3
3.3
CL = 50 pF
0.4 0.8
-0.8 -0.5
2
V
VILD Dynamic Low Voltage
Input (note 1, 3)
3.3
0.8
1) Worst case package
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND
3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz
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74LVQ273M 전자부품, 판매, 대치품
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74LVQ273
WAVEFORM 3: RECOVERY TIME, CLEAR PULSE WIDTH (f=1MHz; 50% duty cycle)
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OCTAL D-TYPE FLIP FLOP WITH CLEAR

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