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PDF 74LVQ273T Data sheet ( Hoja de datos )
| Número de pieza | 74LVQ273T | |
| Descripción | OCTAL D-TYPE FLIP FLOP WITH CLEAR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74LVQ273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX = 150 MHz (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUT
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.4 V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ273 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology. It is ideal for low
power and low noise 3.3V applications.
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ273M
74LVQ273T
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR inputs is held low, the Q
outputs are held low independentely of the other
inputs .
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
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1 page  
74LVQ273
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symb ol
Parameter
T est Con ditio n
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
tPLH Propagation Delay Time
tPHL CK to Q
2.7
3.3(*)
7.5 17.0
6.0 12.0
20.0
14.0
ns
tPHL Propagation Delay Time
CLR to Q
2.7
3.3(*)
10.0 18.0
9.0 13.0
20.0
14.0
ns
tw(L) CLR pulse Width, LOW
2.7
3.3(*)
2.5 7.0
2.0 5.5
8.5 ns
6.0
tw CK pulse Width
2.7
3.3(*)
2.0 7.0
1.5 5.5
8.5 ns
6.0
tsL Setup Time D to CK
tsH HIGH or LOW
2.7
3.3(*)
-0.4 6.5
-0.3 5.0
8.5 ns
6.0
thL Hold Time D to CK
thH HIGH or LOW
2.7
3.3(*)
0.4 3.0
0.3 2.0
3.5 ns
2.5
tREM Recovery Time CLR to
CK
2.7
3.3(*)
-0.1 5.0
0.0 4.0
6.5 ns
4.5
fMAX Maximum Clock
Frequency
2.7
3.3(*)
60 150
50
MHz
90 190
70
tOSLH Output to Output Skew
tOSHL Time (note 1, 2)
2.7
3.3(*)
0.5 1.0
0.5 1.0
1.5 ns
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
CIN Input Capacitance
3.3
5 pF
CPD Power Dissipation
3.3 fIN = 10 MHz
Capacitance (note 1)
30
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8(per FlipFlop)
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5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LVQ273T.PDF ] | |
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