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부품번호 | 74LVQ373M 기능 |
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기능 | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING | ||
제조업체 | STMicroelectronics | ||
로고 | |||
전체 10 페이지수
® 74LVQ373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
s HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE: VOLP = 0.4V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE OUTPUT DRIVE
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2VData Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type latchs are controlled by a
latch enable input (LE) and an output enable
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ373M
74LVQ373T
input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consuption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 1999
1/10
74LVQ373
DC SPECIFICATIONS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
VIH High Level Input Voltage 3.0 to
2.0 2.0
VIL Low Level Input Voltage
3.6
0.8 0.8
VOH High Level Output
Voltage
VOL Low Level Output
Voltage
3.0 VI(* ) = IO=-50 µA 2.9 2.99
2.9
VIH or
VIL
IO=-12 mA
IO=-24 mA
2.58
2.48
2.2
3.0 VI(*) = IO=50 µA
0.002 0.1
0.1
VIH or
VIL
IO=12 mA
IO=24 mA
0 0.36
0.44
0.55
II Input Leakage Current
3.6 VI = VCC or GND
±0.1 ±1
IOZ 3 State Output Leakage
Current
3.6
VI = VIH or VIL
VO = VCC or GND
±0.25
±2.5
ICC Quiescent Supply
Current
3.6 VI = VCC or GND
4 40
IOLD Dynamic Output Current
3.6
VOLD = 0.8 V max
IOHD (note 1, 2)
VOHD = 2 V min
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω.
(*) All outputs loaded.
36
-25
Unit
V
V
V
V
µA
µA
µA
mA
mA
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
VOLP Dynamic Low Voltage
VOLV Quiet Output (note 1, 2)
3.3
0.4 0.8
-0.8 -0.5
VIHD Dynamic High Voltage
Input (note 1, 3)
3.3
CL = 50 pF
2V
VILD Dynamic Low Voltage
Input (note 1, 3)
3.3
0.8
1) Worst case package
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND
3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz
4/10
4페이지 74LVQ373
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: Dn TO Qn PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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7페이지 | |||
구 성 | 총 10 페이지수 | ||
다운로드 | [ 74LVQ373M.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
74LVQ373 | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING | STMicroelectronics |
74LVQ373 | Low Voltage Octal Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |