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부품번호 | 74LVQ373QSC 기능 |
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기능 | Low Voltage Octal Transparent Latch with 3-STATE Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 6 페이지수
May 1998
74LVQ373
Low Voltage Octal Transparent Latch with 3-STATE
Outputs
General Description
The LVQ373 consists of eight latches with 3-STATE outputs
for bus organized system applications. The latches appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is low, the data satisfying the input timing require-
ments is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the bus output is in
the high impedance state.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75Ω
n 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ373SC
74LVQ373SJ
74LVQ373QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC
20-Lead Molded Shrink Small Outline Package, SOIC EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Assignment for
SOIC and QSOP
DS011359-1
IEEE/IEC
DS011359-2
DS011359-3
Pin Descriptions
Pin
Names
D0– D7
LE
OE
O0– O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
© 1998 Fairchild Semiconductor Corporation DS011359
www.fairchildsemi.com
AC Electrical Characteristics
Symbol
Parameter
VCC
(V)
TA = +25˚C
CL = 50 pF
TA = −40˚C to +85˚C
CL = 50 pF
Units
Min Typ Max Min Max
tPHL
tPLH
tPLH
tPHL
tPZL
tPZH
tPHZ
tPLZ
tOSHL
tOSLH
Propagation Delay
Dn to On
Propagation Delay
LE to On
Output Enable Time
Output Disable Time
Output to Output Skew
(Note 9)
2.7 2.5 9.6 14.8 2.5 16.0 ns
3.3 ±0.3
2.5
8.0 10.5 2.5 11.0
2.7 2.5 9.6 16.9 2.5 18.0 n
3.3 ±0.3
2.5
8.0 12.0 2.5 12.5
2.7 2.5 10.2 18.3 2.5 19.0 ns
3.3 ±0.3
2.5
8.5 13.0 2.5 13.5
2.7 1.0 10.8 20.4 1.0 21.0 ns
3.3 ±0.3
1.0
9.0 14.5 1.0 15.0
2.7
1.0 1.5
1.5 ns
3.3 ±0.3
1.0 1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
Symbol
Parameter
tS Setup Time, HIGH or LOW
tH Hold Time, HIGH or LOW
tW LE Pulse Width, HIGH
VCC
(V)
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
Capacitance
Symbol
Parameter
CIN
CPD (Note 10)
Input Capacitance
Power Dissipation Capacitance
Note 10: CPD is measured at 10 MHz.
TA = +25˚C
CL = 50 pF
Typ
TA = −40˚C to +85˚C
CL = 50 pF
Guaranteed Minimum
0 4.0
4.5
0 3.0
3.0
0 1.5
1.5
0 1.5
1.5
2.4 5.0
6.0
2.0 4.0
4.0
Units
ns
ns
ns
Typ Units
Conditions
4.5 pF VCC = Open
39 pF VCC = 3.3V
www.fairchildsemi.com
4
4페이지 | |||
구 성 | 총 6 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
74LVQ373QSC | Low Voltage Octal Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
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