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74LVQ573M PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 74LVQ573M
기능 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING
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74LVQ573M 데이터시트, 핀배열, 회로
® 74LVQ573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s LOW NOISE:
VOLP = 0.5 V (TYP.) at VCC = 3.3V
s 75TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s PCI BUS LEVELS GUARANTEED AT 24mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and low
noise 3.3V applications.
These 8 bit D-Type flip-flops are controlled by a
latch enable input (LE) and an output enable
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ573M
74LVQ573T
input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 1999
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74LVQ573M pdf, 반도체, 판매, 대치품
74LVQ573
DC SPECIFICATIONS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
VIH High Level Input Voltage 3.0 to
2.0 2.0
VIL Low Level Input Voltage
3.6
0.8 0.8
VOH High Level Output
Voltage
VOL Low Level Output
Voltage
3.0 VI(* ) = IO=-50 µA 2.9 2.99
2.9
VIH or
VIL
IO=-12 mA
IO=-24 mA
2.58
2.48
2.2
3.0 VI(*) = IO=50 µA
0.002 0.1
0.1
VIH or
VIL
IO=12 mA
IO=24 mA
0 0.36
0.44
0.55
II Input Leakage Current
3.6 VI = VCC or GND
±0.1 ±1
IOZ 3 State Output Leakage
Current
3.6
VI = VIH or VIL
VO = VCC or GND
±0.25
±2.5
ICC Quiescent Supply
Current
3.6 VI = VCC or GND
4 40
IOLD Dynamic Output Current
IOHD (note 1, 2)
3.6
VOLD = 0.8 V max
VOHD = 2 V min
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 .
(*) All outputs loaded.
36
-25
Unit
V
V
V
V
µA
µA
µA
mA
mA
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
Test Conditions
VCC
(V)
Valu e
TA = 25 oC
-40 to 85 oC
Min. T yp. Max. Min. Max.
Unit
VOLP
VOLV
VIHD
Dynamic Low Voltage
Quiet Output (note 1, 2)
Dynamic High Voltage
Input (note 1, 3)
3.3
3.3
CL = 50 pF
0.5 0.8
-0.8 -0.6
2
V
VILD Dynamic Low Voltage
Input (note 1, 3)
3.3
0.8
1) Worst case package
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND
3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz
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74LVQ573M 전자부품, 판매, 대치품
74LVQ573
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: Dn TO Qn PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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