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74LVQ573SJ PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 74LVQ573SJ
기능 Low Voltage Octal Latch with 3-STATE Outputs
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74LVQ573SJ 데이터시트, 핀배열, 회로
May 1998
74LVQ573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVQ573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output Enable
(OE) inputs. The LVQ573 is functionally identical to the
LVQ373 but with inputs and outputs on opposite sides of the
package.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ, and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75
n 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ573SC
74LVQ573SJ
74LVQ573QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC and QSOP
DS011361-1
IEEE/IEC
DS011361-2
DS011361-3
Pin Descriptions
Pin Names
D0– D7
LE
OE
O0– O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
© 1998 Fairchild Semiconductor Corporation DS011361
www.fairchildsemi.com




74LVQ573SJ pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
VCC
(V)
TA = +25˚C
CL = 50 pF
TA = −40˚C to +85˚C
CL = 50 pF
Units
Min Typ
Max Min Max
tPHL
tPLH
tPLH
tPHL
tPZL
tPZH
tPHZ
tPLZ
tOSHL
tOSLH
Propagation Delay
Dn to On
Propagation Delay
LE to On
Output Enable Time
Output Disable Time
Output to Output Skew (Note 9)
Dn to On
2.7 2.5 10.2 14.8 2.5 16.0
3.3 ±0.3 2.5 8.5 10.5 2.5 11.0
2.7 2.5 10.2 16.9 2.5 18.0
3.3 ±0.3 2.5 8.5 12.0 2.5 12.5
2.7 2.5 10.2 18.3 2.5 19.0
3.3 ±0.3 2.5 8.5 13.0 2.5 13.5
2.7 1.0 10.8 20.4 1.0 21.0
3.3 ±0.3 1.0 9.0 14.5 1.0 15.0
2.7
1.0 1.5
1.5
3.3 ±0.3
1.0 1.5
1.5
ns
ns
ns
ns
ns
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
Symbol
tS
tH
tW
Parameter
Setup Time, HIGH or LOW
Dn to LE
Hold Time, HIGH or LOW
Dn to LE
LE Pulse Width, HIGH
VCC
(V)
2.7
3.3 ±0.3
2.7
3.3 ±0.3
2.7
3.3 ±0.3
TA = +25˚C
CL = 50 pF
Typ
TA = −40˚C to +85˚C
CL = 50 pF
Guaranteed Minimum
0 4.0
4.5
0 3.0
3.0
0 1.5
1.5
0 1.5
1.5
2.4 5.0
6.0
2.0 4.0
4.0
Units
ns
ns
ns
Capacitance
Symbol
Parameter
CIN
CPD (Note 10)
Input Capacitance
Power Dissipation Capacitance
Note 10: CPD is measured at 10 MHz.
Typ
4.5
37
Units
pF
pF
Conditions
VCC = Open
VCC = 3.3V
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부품번호상세설명 및 기능제조사
74LVQ573SC

Low Voltage Octal Latch with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor
74LVQ573SJ

Low Voltage Octal Latch with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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