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부품번호 74LVT16245 기능
기능 Low Voltage 16-Bit Transceiver with 3-STATE Outputs
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74LVT16245 데이터시트, 핀배열, 회로
January 1999
Revised November 1999
74LVT16245 74LVTH16245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
General Description
The LVT16245 and LVTH16245 contain sixteen non-invert-
ing bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVTH16245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-volt-
age (3.3V) VCC applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT16245
and LVTH16245 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH16245), also
available without bushold feature (74LVT16245).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 16245
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
Package
Number
Package Description
74LVT16245MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300Wide
74LVT16245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16245MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300Wide
74LVTH16245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS500152
www.fairchildsemi.com




74LVT16245 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Symbol
Parameter
IOZH (Note 3) 3-STATE Output Leakage Current
IOZH+
3-STATE Output Leakage Current
ICCH
Power Supply Current
ICCL Power Supply Current
ICCZ
Power Supply Current
ICCZ+
Power Supply Current
VCC
TA = −40°C to +85°C
Units
(V) Min Max
3.6 5 µA
3.6 10 µA
3.6
0.19
mA
3.6 5.0 mA
3.6
0.19
mA
3.6 0.19 mA
ICC
Increase in Power Supply Current
(Note 6)
3.6
0.2 mA
Note 3: Applies to bushold versions only (74LVTH16245).
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
VO = 3.6V
VCC < VO 5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
VCC VO 5.5V,
Outputs Disabled
One Input at VCC 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 7)
Symbol
Parameter
VCC TA = 25°C
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
VOLV
Quiet Output Minimum Dynamic VOL
3.3
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
0.8
0.8
Note 8: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
Units
V
V
Conditions
CL = 50 pF, RL = 500
(Note 8)
(Note 8)
AC Electrical Characteristics
TA = −40°C to +85°C
Symbol
Parameter
CL = 50 pF, RL = 500
VCC = 3.3V ± 0.3V
VCC = 2.7V
Units
Min Max Min Max
tPLH Propagation Delay Data to Output
tPHL
1.5 3.5
1.3 3.5
1.5 3.9
1.3 3.9
ns
tPZH
tPZL
Output Enable Time
1.5 4.5
1.6 5.3
1.5 5.3
1.6 6.9
ns
tPHZ
tPLZ
Output Disable Time
2.3 5.4
2.2 5.1
2.3 6.1
2.2 5.4
ns
tOSHL
tOSLH
Output to Output Skew
(Note 9)
1.0 1.0 ns
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance (Note 10)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
CI/O
Input/Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
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