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74LVT16245B 데이터시트 PDF




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부품번호 74LVT16245B 기능
기능 3.3 V 16-bit transceiver
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74LVT16245B 데이터시트, 핀배열, 회로
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
Rev. 10 — 1 March 2012
Product data sheet
1. General description
The 74LVT16245B; 74LVTH16245B is a high-performance BiCMOS product designed for
VCC operation at 3.3 V.
This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. The device features an output enable input (nOE) for easy
cascading and a direction input (nDIR) for direction control.
2. Features and benefits
16-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V




74LVT16245B pdf, 반도체, 판매, 대치품
NXP Semiconductors
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVT16245B
74LVTH16245B
1DIR 1
1B0 2
1B1 3
GND 4
1B2 5
1B3 6
VCC 7
1B4 8
1B5 9
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
VCC 18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2DIR 24
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCC
41 1A4
40 1A5
39 GND
38 1A6
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 VCC
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OE
001aae471
Fig 3. Pin configuration for SSOP48 and TSSOP48
74LVT16245B
123456
A 1DIR n.c. n.c. n.c. n.c. 1OE
B 1B1 1B0 GND GND 1A0 1A1
C 1B3 1B2 VCC VCC 1A2 1A3
D 1B5 1B4 GND GND 1A4 1A5
E 1B7 1B6
1A6 1A7
F 2B0 2B1
2A1 2A0
G 2B2 2B3 GND GND 2A3 2A2
H 2B4 2B5 VCC VCC 2A5 2A4
J 2B6 2B7 GND GND 2A7 2A6
K 2DIR n.c. n.c. n.c. n.c. 2OE
001aae474
Transparent top view
Fig 4. Pin configuration for VFBGA56
74LVT_LVTH16245B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 1 March 2012
© NXP B.V. 2012. All rights reserved.
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74LVT16245B 전자부품, 판매, 대치품
NXP Semiconductors
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
VI input voltage
VO output voltage
output in OFF-state or
HIGH-state
0.5
[1] 0.5
[1] 0.5
+4.6
+7.0
+7.0
V
V
V
IIK
input clamping current
VI < 0 V
50 -
mA
IOK
output clamping current
VO < 0 V
50 -
mA
IO output current
output in LOW-state
output in HIGH-state
- 128 mA
64 -
mA
Tstg storage temperature
65
+150
C
Tj junction temperature
[2] -
150 C
Ptot
total power dissipation
Tamb = 40 C to +85 C;
(T)SSOP48 package
[3] -
500 mW
VFBGA56 package
[4] -
1 000
mW
HXQFN60 package
[4] -
1 000
mW
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VCC
VI
VIH
VIL
IOH
IOL
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
none
ambient temperature
current duty cycle 50 %;
fi 1 kHz
in free-air
input transition rise and fall rate outputs enabled
Min Typ Max Unit
2.7 -
3.6 V
0-
5.5 V
2.0 - - V
- - 0.8 V
32 - - mA
- - 32 mA
- - 64 mA
40 -
--
+85 C
10 ns/V
74LVT_LVTH16245B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 1 March 2012
© NXP B.V. 2012. All rights reserved.
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