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부품번호 | 74LVT16373MEA 기능 |
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기능 | Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 7 페이지수
January 1999
Revised April 1999
74LVT16373 • 74LVTH16373
Low Voltage 16-Bit Transparent Latch with
3-STATE Outputs
General Description
The LVT16373 and LVTH16373 contain sixteen non-invert-
ing latches with 3-STATE outputs and is intended for bus
oriented applications. The device is byte controlled. The
flip-flops appear transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The LVTH16373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT16373 and LVTH16373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V
VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH16373), also
available without bushold feature (74LVT16373).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 16373
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
Package
Number
Package Descripion
74LVT16373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS012021.prf
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Symbol
VCC
VI
VO
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
IIK DC Input Diode Current
IOK DC Output Diode Current
IO DC Output Current
ICC
IGND
TSTG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−50
−50
64
128
±64
±128
−65 to +150
Recommended Operating Conditions
Conditions
Output in 3-STATE
Output in HIGH or LOW State (Note 2)
VI < GND
VO < GND
VO > VCC Output at HIGH State
VO > VCC Output at LOW State
Units
V
V
V
mA
mA
mA
mA
mA
°C
Symbol
Parameter
Min Max Units
VCC Supply Voltage
2.7 3.6
V
VI Input Voltage
0 5.5
V
IOH HIGH Level Output Current
−32 mA
IOL LOW Level Output Current
64 mA
TA Free-Air Operating Temperature
−40 85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0 10 ns/V
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
VIK
VIH
VIL
VOH
VOL
II(HOLD)
(Note 4)
II(OD)
(Note 4)
II
IOFF
IPU/PD
IOZL
IOZH
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
Power Off Leakage Current
Power up/down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
VCC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
T A = −40°C to +85°C
Min Typ Max
(Note 3)
−1.2
2.0
0.8
VCC − 0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
−75
500
−500
10
±1
−5
1
±100
±100
−5
5
Units
Conditions
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
II = −18 mA
VO ≤ 0.1V or
VO ≥ VCC − 0.1V
IOH = −100 µA
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
VI = 0.8V
VI = 2.0V
(Note 5)
(Note 6)
VI = 5.5V
VI = 0V or VCC
VI = 0V
VI = VCC
0V ≤ VI or VO ≤ 5.5V
VO = 0.5V to 3.0V
VI = GND or VCC
VO = 0.5V
VO = 3.0V
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4
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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구 성 | 총 7 페이지수 | ||
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74LVT16373MEA | Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
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