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PDF 74LVT2244 Data sheet ( Hoja de datos )
| Número de pieza | 74LVT2244 | |
| Descripción | Low Voltage Octal Buffer/Line Driver | |
| Fabricantes | Fairchild Semiconductor | |
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February 2008
74LVT2244, 74LVTH2244
Low Voltage Octal Buffer/Line Driver with 3-STATE
Outputs and 25Ω Series Resistors in the Outputs
Features
■ Input and output interface capability to systems at
5V VCC
■ Equivalent 25Ω-Series resistors on outputs
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH2244),
also available without bushold feature (74LVT2244)
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs source/sink –12mA/+12mA
■ Latch-up performance exceeds 500mA
■ ESD performance:
– Human-body model > 2000V
– Machine model > 200V
– Charged-device model > 1000V
General Description
The LVT2244 and LVTH2244 are octal buffers and line
drivers designed to be employed as memory address
drivers, clock drivers and bus oriented transmitters or
receivers which provides improved PC board density.
The equivalent 25Ω-Series resistors helps reduce output
overshoot and undershoot.
The LVTH2244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal buffers and line drivers are designed for low-
voltage (3.3V) VCC applications, but with the capability to
provide a TTL interface to a 5V environment. The
LVT2244 and LVTH2244 are fabricated with an
advanced BiCMOS technology to achieve high speed
operation similar to 5V ABT while maintaining low power
dissipation.
Ordering Information
Order Number
74LVT2244WM
74LVT2244SJ
74LVT2244MTC
74LVTH2244WM
74LVTH2244SJ
74LVTH2244MTC
Package
Number
M20B
M20D
MTC20
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74LVT2244, 74LVTH2244 Rev. 1.5.0
www.fairchildsemi.com
1 page  
Dynamic Switching Characteristics(7)
Symbol
Parameter
VOLP
VOLV
Quiet Output Maximum
Dynamic VOL
Quiet Output Minimum
Dynamic VOL
Conditions
VCC (V) CL = 50pF, RL = 500Ω
3.3 (8)
TA = 25°C
Min. Typ. Max.
0.8
3.3 (8)
–0.8
Notes:
7. Characterized in SOIC package. Guaranteed parameter, but not tested.
8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.
Units
V
V
AC Electrical Characteristics
Symbol
Parameter
TA = –40°C to +85°C,
CL = 50pF, RL = 500Ω
VCC = 3.3V ± 0.3V
Min. Typ.(9) Max.
VCC = 2.7V
Min. Max.
Units
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL, tOSLH
Propagation Delay Data to Output
Output Enable Time
Output Disable Time
Output to Output Skew(10)
1.0
1.0
1.0
1.1
1.9
1.8
4.4 1.0 5.3 ns
4.1 1.0 4.4
5.9 1.0 7.7 ns
5.5 1.1 6.2
6.1 1.9 6.8 ns
4.5 1.8 4.5
1.0 1.0 ns
Notes:
9. All typical values are at VCC = 3.3V, TA = 25°C.
10. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance(11)
Symbol
Parameter
Conditions
Typical
CIN
COUT
Input Capacitance
Output Capacitance
VCC = 0V, VI = 0V or VCC
VCC = 3.0V, VO = 0V or VCC
3
6
Note:
11. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883B, Method 3012.
Units
pF
pF
©1999 Fairchild Semiconductor Corporation
74LVT2244, 74LVTH2244 Rev. 1.5.0
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74LVT2244.PDF ] | |
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