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74LVT240MTC 데이터시트 PDF




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부품번호 74LVT240MTC 기능
기능 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
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74LVT240MTC 데이터시트, 핀배열, 회로
July 1999
Revised August 1999
74LVT240 • 74LVTH240
Low Voltage Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT240 and LVTH240 are inverting octal buffers and
line drivers designed to be employed as memory address
drivers, clock drivers and bus oriented transmitters or
receivers which provides improved PC board density.
The LVTH240 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal buffers and line drivers are designed for low-
voltage (3.3V) VCC applications, but with the capability to
provide a TTL interface to a 5V environment. The LVT240
and LVTH240 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH240), also
available without bushold feature (74LVT240).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 240
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVT240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LVT240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT240MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVT240MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LVTH240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH240MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVTH240MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS500153
www.fairchildsemi.com




74LVT240MTC pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Symbol
Parameter
IOZH+
ICCH
ICCL
ICCZ
ICCZ+
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
T A =−40°C to +85°C
VCC
(V)
Min
Typ
Max
Units
(Note 3)
3.6 10 µA
3.6
0.19
mA
3.6 5 mA
3.6
0.19
mA
3.6
0.19
mA
ICC
Increase in Power Supply Current
(Note 7)
3.6
0.2 mA
Note 3: All typical values are at VCC = 3.3V, TA = 25°C.
Note 4: Applies to bushold versions only (74LVTH240).
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
VCC < VO 5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
VCC VO 5.5V,
Outputs Disabled
One Input at VCC 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 8)
Symbol
Parameter
VCC TA = 25°C
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
VOLV
Quiet Output Minimum Dynamic VOL
3.3
Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.
0.8
0.8
Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
Units
V
V
Conditions
CL = 50 pF, RL = 500
(Note 9)
(Note 9)
AC Electrical Characteristics
TA = −40°C to +85°C
CL = 50 pF, RL = 500
Symbol
Parameter
VCC = 3.3V ±0.3V
VCC = 2.7V
Units
Min Typ Max Min Max
(Note 10)
tPLH Propagation Delay Data to Output
tPHL
1.1
1.3
3.8 1.1 4.6
ns
4.0 1.3 4.2
tPZH Output Enable Time
1.1
4.6 1.1 5.6
ns
tPZL 1.4 4.4 1.4 5.1
tPHZ Output Disable Time
2.0
4.5 2.0 4.7
ns
tPLZ 1.8 4.3 1.8 4.3
tOSHL
tOSLH
Output to Output Skew
(Note 11)
1.0 1.0 ns
Note 10: All typical values are at VCC = 3.3V, TA = 25°C.
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
3
6
Units
pF
pF
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74LVT240MTC 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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74LVT240MTC

Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

Fairchild Semiconductor
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