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부품번호 74LVTH16244MEA 기능
기능 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
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74LVTH16244MEA 데이터시트, 핀배열, 회로
March 1999
Revised April 1999
74LVT16244 • 74LVTH16244
Low Voltage16-Bit Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT16244 and LVTH16244 contain sixteen non-invert-
ing buffers with 3-STATE outputs designed to be employed
as a memory and address driver, clock driver, or bus ori-
ented transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
The LVTH16244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16244 and
LVTH16244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation
Features
s Input and output interface capability to systems at 5V
VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH16244), also
available without bushold feature (74LVT16244).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 16244
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
Package
Number
Package Description
74LVT16244MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT16244MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16244MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH16244MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS500151
Print form created on April 12, 1999 2:43 pm
www.fairchildsemi.com




74LVTH16244MEA pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Symbol
Parameter
IOZH+
ICCH
ICCL
ICCZ
ICCZ+
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
TA = −40°C to +85°C
VCC
(V)
Min
Typ
Max
Units
(Note 3)
3.6 10 µA
3.6
0.19
mA
3.6 5.0 mA
3.6
0.19
mA
3.6
0.19
mA
ICC
Increase in Power Supply Current
(Note 7)
3.6
0.2 mA
Note 3: All typical values are at VCC = 3.3V, TA = 25°C.
Note 4: Applies tobushold versions only (LVTH16244).
Note 5: An external driver must source at least the specified current to switch from LOW to HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH to LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
VCC < VO 5.5V
Outputs High
Outputs Low
Outputs Disabled
VCC VO 5.5V,
Outputs Disabled
One Input at VCC 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 8)
Symbol
Parameter
VCC TA = 25°C
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
VOLV
Quiet Output Minimum Dynamic VOL
3.3
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested.
0.8
0.8
Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
Units
V
V
Conditions
CL = 50 pF, RL = 500
(Note 9)
(Note 9)
AC Electrical Characteristics
TA = −40°C to +85°C
CL = 50 pF, RL = 500
Symbol
Parameter
VCC = 3.3V ±0.3V
VCC = 2.7V
Units
Min Typ Max Min Max
(Note 10)
tPLH Propagation Delay Data to Output
tPHL
1.2
1.2
3.5 1.2 3.9
ns
3.5 1.2 3.9
tPZH
tPZL
Output Enable Time
1.2 4.0 1.2 5.0
ns
1.2 5.0 1.2 6.5
tPHZ
tPLZ
Output Disable Time
2.0 4.7 2.0 5.2
ns
1.5 4.2 1.5 4.4
tOSHL
Output to Output Skew
1.0 1.0 ns
tOSLH
(Note 11)
Note 10: All typical values are at VCC = 3.3V, TA = 25°C.
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH).
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
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74LVTH16244MEA

Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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