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부품번호 | 74LVTH16500MEA 기능 |
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기능 | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
Preliminary
May 2000
Revised May 2000
74LVTH16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16500 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LVTH16500 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceiver is designed for low voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16500 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 16500
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH16500MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16500MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS012447
www.fairchildsemi.com
Preliminary
DC Electrical Characteristics
Symbol
Parameter
VIK Input Clamp Diode Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
II(HOLD)
Bushold Input Minimum Drive
VCC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
2.7
2.7
3.0
3.0
3.0
3.0
II(OD)
II
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
3.0
3.6
3.6
3.6
IOFF
IPU/PD
IOZL
IOZH
IOZH+
ICCH
ICCL
ICCZ
ICCZ+
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
T A = −40°C to +85°C
Min Max
−1.2
2.0
0.8
VCC − 0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
−75
500
−500
10
±1
−5
1
±100
±100
−5
5
10
0.19
5
0.19
0.19
Units
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
∆ICC
Increase in Power Supply Current
(Note 8)
3.6
0.2 mA
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 9)
Symbol
Parameter
VCC TA = 25°C
Units
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
3.3
−0.8
V
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
Conditions
II = −18 mA
VO ≤ 0.1V or
VO ≥ VCC − 0.1V
IOH = −100 µA
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
VI = 0.8V
VI = 2.0V
(Note 6)
(Note 7)
VI = 5.5V
VI = 0V or VCC
VI = 0V
VI = VCC
0V ≤ VI or VO ≤ 5.5V
VO = 0.5V to 3.0V
VI = GND or VCC
VO = 0.0V
VO = 3.6V
VCC < VO ≤ 5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Conditions
CL = 50 pF, RL = 500Ω
(Note 10)
(Note 10)
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4페이지 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Preliminary
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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부품번호 | 상세설명 및 기능 | 제조사 |
74LVTH16500MEA | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary | Fairchild Semiconductor |
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