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74LVTH16646MTD 데이터시트 PDF




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부품번호 74LVTH16646MTD 기능
기능 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
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74LVTH16646MTD 데이터시트, 핀배열, 회로
January 2000
Revised January 2000
74LVTH16646
Low Voltage 16-Bit Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH16646 contains sixteen non-inverting bidirec-
tional registered bus transceivers providing multiplexed
transmission of data directly from the input bus or from the
internal storage registers. Each byte has separate control
inputs which can be shorted together for full 16-bit opera-
tion. The DIR inputs determine the direction of data flow
through the device. The CPAB and CPBA inputs load data
into the registers on the LOW-to-HIGH transition (see
Functional Description).
The LVTH16646 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These transceivers are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH16646 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintaining
low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides
glitch-free bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 16646
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH16646MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16646MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2000 Fairchild Semiconductor Corporation DS012023
www.fairchildsemi.com




74LVTH16646MTD pdf, 반도체, 판매, 대치품
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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74LVTH16646MTD 전자부품, 판매, 대치품
AC Electrical Characteristics
TA = −40°C to +85°C
Symbol
Parameter
CL = 50 pF, RL = 500
VCC = 3.3 ± 0.3V
VCC = 2.7V
Units
Min Max Min Max
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
Maximum Clock Frequency
Propagation Delay
CPAB or CPBA to A or B
Propagation Delay
Data to A or B
Propagation Delay
SBA or SAB to A or B
Output Enable Time
OE to A or B
150 150 MHz
1.3 5.4 1.3 5.9
1.3 5.2 1.3 5.8
ns
1.0 4.4 1.0 4.7
ns
1.0 4.6 1.0 5.1
1.0 4.6 1.0 5.4
1.0 4.8 1.0 5.6
ns
1.0 4.7
1.0 5.1
1.0 5.4
1.0 6.0
ns
tPHZ Output Disable Time
tPLZ OE to A or B
2.0 5.6
2.0 5.4
2.0 6.1
2.0 6.1
ns
tPZH Output Enable Time
tPZL DIR to A or B
1.0 4.9
1.0 5.4
1.0 5.4
1.0 6.4
ns
tPHZ Output Disable Time
tPLZ DIR to A or B
1.5 6.4
1.5 5.4
1.5 7.1
1.5 5.9
ns
tW Pulse Duration
CPAB or CPBA HIGH or LOW
3.3
3.3
ns
tS
Setup Time
A or B before CPAB or CPBA, Data HIGH
1.2
A or B before CPAB or CPBA, Data LOW
2.0
1.5
2.8
ns
tH Hold Time
A or B after CPAB or CPBA, Data HIGH
A or B after CPAB or CPBA, Data LOW
0.5
0.5
0.0
0.5
ns
tOSHL
tOSLH
Output to Output Skew (Note 9)
1.0 1.0
ns
1.0 1.0
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = Open, VI = 0V or VCC
CI/O Input/Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
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부품번호상세설명 및 기능제조사
74LVTH16646MTD

Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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